View XR21B1422IL40-F_8648881.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2014 exar corporation xr21b1422 enhanced 2-ch full-speed usb uart exar.com/xr21b1422 rev 1a 1 / 60 general description the xr21b1422 is an enhanced universal asynchronous receiver and transmitter (uart) bridge to usb interface. the usb interface is fully compliant to the usb 2.0 (full-speed) specification with 12 mbps usb data transfer rate. the usb interface also supports usb suspend, resume and remote wakeup operations. the usb vendor id, product id, power mode, remote wakeup support, maximum power, and numerous other settings may be programmed in the on-chip otp memory via the usb interface. the xr21b1422 includes an internal oscillator and does not require an external crystal/oscillator. any uart baud rate up to 12 mbps may be generated with this internal clock and the fractional baud rate generator. the uart pins for each port may also be configured as gpio; direction, state, output driver type and input pull-up or pull-down resistors are pro- grammed either through on chip otp, or on the fly via memory mapped registers. large 512-byte tx and rx fifos prevent buffer overflow errors and opti- mize data throughput. automatic half-duplex direction control and optional multi drop (9-bit) mode si mplify both hardware and software in half-duplex rs-485 applications. the xr21b1422 uses the native os cdc-acm driver or an exar supplied custom driver. exar provides whql/hck-certified software drivers for windows 2000, xp, vista, 7, 8, 8.1 as well as software drivers for windows ce, linux and mac os x. full source code is available. the xr21b1422 operates from a single 5v or 3.3v power supply. when powered with 5v input, a regulated 3.3v output is supplied. features ? 15kv esd on usbd+/usbd- ? usb 2.0 compliant, full-speed (12mbps) ? unique pre-programme d usb serial number ? internally generate d 48mhz core clock ? enhanced uart features ? baud rates up to 12 mbps ? fractional baud rate generator ? 512-byte tx and 512-byte rx fifos ? auto hardware / software flow control ? multidrop and half-duplex modes ? auto rs-485 half-duplex control ? selectable gpio or modem i/o ? up to 10 gpios per channel ? 5v tolerant gpio inputs ? suspend state gpio configuration ? configurable clock output ? 40-pin qfn package ? industrial -40 c to +85 c temperature range applications ? building automation ? security systems ? factory and process control ? atm terminals ? usb to serial controllers ordering information C page 60 block diagram usb slave interface 512-byte tx fifo gpios/ modem io internal oscillator (48mhz) 512-byte rx fifo uart ch a fractional brg internal status and control registers otp usb descriptors ldo 3v3 uart ch b (same as ch a) usb tx rx vio 0k 230k 460k 690k 920k 1150k 1380k 1610k 1840k 230k 460k 920k 1840k data rate (bps) throughput comparison competitor exar
? 2014 exar corporation xr21b1422 2 / 60 exar.com/xr21b1422 rev 1a absolute maximum ratings stresses beyond the limits listed below may cause perma- nent damage to the device. exposure to any absolute max- imum rating condition for extended periods may affect device reliability and lifetime. supply voltage (vcc_reg)......................................+5.75v supply voltage (vcc, vio)............................................+4v input voltage (vbus_sense).......................-0.3 to +5.75v input voltage (all other pins)............................-0.3 to +5.6v junction temperature.................................................125c operating conditions operating temperature range.....................-40c to +85c electrical characteristics unless otherwise noted: t a = -40c to +85c, vcc_reg = +4.4v to +5.25v or +3.0v to +3.6v, vio = +1.8v to +3.6v. symbol parameter conditions min typ max units power i cc power supply current vcc_reg = +4.4v to +5.25v 15 23 ma i susp lowpower mode current 0.85 1.25 ma v out regulated output voltage (vcc pin) vcc_reg = +4.4v to +5.25v. maximum output current = 200 ma including the supply current of the xr21b1422. 33.33.6 v uart, usb_stat and gpio pins v il input low voltage -0.3 0.25* vio v v ih input high voltage 0.70* vio 5.5 v v ol output low voltage iol = 1ma, vio = +1.6v 0.3 v iol = 4ma, vio = +3.6v 0.5 v v oh output high voltage ioh = -400ua, vio = +1.6v 1.3 vio v ioh = -1.5ma, vio = +3.6v 2.8 vio v i il input low leakage current vio = +3v to +3.6v, vcc_reg = +4.4v to +5.25v, v input = 0v 10 a i ih input high leakage current vio = +3v to +3.6v, vcc_reg = +4.4v to +5.25v, v input = +3.3v 10 a vio = +3v to +3.6v, vcc_reg = +4.4v to +5.25v, v input = +5.5v 120 a c in input pin capacitance 5pf
? 2014 exar corporation xr21b1422 3 / 60 exar.com/xr21b1422 rev 1a usb i/o pins v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 5.5 v v ol output low voltage external 15k to gnd on usbd+ and usbd- pins 00.3v v oh output high voltage external 15k to gnd on usbd+ and usbd- pins 2.8 3.6 v v drvz driver output impedance 28 44 symbol parameter conditions min typ max units
? 2014 exar corporation xr21b1422 4 / 60 exar.com/xr21b1422 rev 1a pin configuration 20 19 18 17 16 15 14 13 12 11 31 32 33 34 35 36 37 38 39 40 10 9 8 7 6 5 4 3 2 1 21 22 23 24 25 26 27 28 29 30 gpioa8/txta gpioa9/rxta nc nc gnd usbd+ usbd- vio vcc vcc_reg gpiob0/rib#/rwkb# gpiob1/cdb# gpiob2/dsrb# gpiob3/dtrb# gpiob4/ctsb# gnd vio gpiob5/rtsb#/rs485b rxb txb e_pad exar xr21b1422 gpioa7/rs485a gpioa6/clka txa rxa gpioa5/rtsa#/rs485a gpioa4/ctsa# gpioa3/dtra# gpioa2/dsra# gpioa1/cda# gpioa0/ria#/rwka# vbus_sense reset# nc usb_stat2 usb_stat1 gpiob9/rxtb gpiob8/txtb gpiob7/rs485b gpiob6/clkb nc
? 2014 exar corporation xr21b1422 5 / 60 exar.com/xr21b1422 rev 1a pin assignments pin no. pin name type description 1 gpioa8/txta i/o general purpose i/o, or uart transmit data i ndicator. defaults to gpio input with internal pull- up resistor. see txt and rxt pins on page 18 . when configured as transmit indicator, this pin will toggle at ~10hz intervals while the uart is transmitting data. 2 gpioa9/rxta i/o general purpose i/o, or uart receive data indicator. defaults to gpio input with internal pull- up resistor. see txt and rxt pins on page 18 . when configured as receive indicator, this pin will toggle at ~10hz intervals while the uart is receiving data. 3 nc - no connect. 4 nc - no connect. 5 gnd pwr power supply common, ground. 6 usbd+ i/o usb port differential data positive. this pin has internal pull-up resistor compliant to the usb 2.0 specification. the esd prot ection on this pin is 15kv hbm. 7 usbd- i/o usb port differential data negative. the esd protection on this pin is 15kv hbm. 8 vio pwr i/o voltage input to the uart/gpio pins. must be between 1.8 and 3.6v. may be connected to vcc (pin 12) if vcc_reg input voltage is 5v. see usb power modes on page 11. 9 vcc pwr 3.3v power to the device, or 3.3v power out put from the device when 5v power is supplied to vcc_reg pin. 3.3v output power can source up to 200 ma maximum (including the device) and should be decoupled by minimum of 4.7f ceramic capacitor. see usb power modes on page 11. 10 vcc_reg pwr 5v or 3.3v power to the device. in bus-powered mode, connect vbus power from the usb host to this pin and to the vbus_sense pin. see figure 1 . in self-powered mode, connect on-board 5v or 3.3v source to this pin and vbus from the usb host to the vbus_sense pin. see figure 2 and figure 3 . 11 vbus_sense i must be connected to vbus power from t he usb host pc. this pin is used to disable the inter- nal pull-up resistor on the usbd+ signal when vbus is not present. 12 reset# i/o od active low open drain output. asserted at power on or any time device is reset by either regis- ter or usb bus reset. as an input, must be asserted for at least 15s to force a device reset. reset pulse width input of shorter than 15s will have unknown effects. a weak internal pull-up resistor provides noise immunity if left unconnected. 13 nc - no connect. 14 usb_stat2 o / od this pin has the sa me functionality as the usb_stat1 pin. however, the default output for this pin is active low polarity, asserted whenever the xr21b1422 is placed into a suspended state. this default may be changed via the pin_cfg_usb_stat2 register. 15 usb_stat1 o the usb_stat1 output pin may be used to indicate any of three usb status conditions: 1. usb_stat1 is asserted when the usb host asserts usb reset. 2. usb_stat1 is asserted when the usb host pc places the xr21b1422 device into the sus- pend state. 3. usb_stat1 is asserted when it is not safe to draw the amount of current requested in the device maximum power field of the configuration descriptor. a. for a low power device (<=1 unit load or 100ma, bmaxpower <= 0x32), usb_stat1 will be asserted when the usb uart is in the suspend mode or when it is not yet configured. b. for a high power device (bmaxpower > 0x32), usb_stat1 will be asserted when the usb uart is in the suspend mode or when it is not yet configured. the assertion polarity and status condition are selectable via the pin_cfg_stat1 register. the usb_stat pin will be de-asserted whenever the selected condition(s) is/are not met. the default output for this pin is active high polar ity, asserted whenever the xr21b1422 is placed into a suspended state.
? 2014 exar corporation xr21b1422 6 / 60 exar.com/xr21b1422 rev 1a 16 gpiob9/rxtb i/o general purpose i/o, or uart receive data indicator. defaults to gpio input with internal pull- up resistor. see txt and rxt pins on page 18 . when configured as receive indicator, this pin will toggle at ~10hz intervals while the uart is receiving data. 17 gpiob8/txtb i/o general purpose i/o, or uart transmit data i ndicator. defaults to gpio input with internal pull- up resistor. see txt and rxt pins on page 18 . when configured as transmit indicator, this pin will toggle at ~10hz intervals while the uart is transmitting data. 18 gpiob7/rs485b i/o general purpose i/o, or auto rs-485 half-d uplex control. defaults to gpio input with internal pull-up resistor. 19 gpiob6/clkb i/o general purpose i/o, or clock or pulse output. defaults to gpio input with internal pull-up resistor. see programmable output clock on page 15 . 20 nc - no connect. 21 txb o uart transmit data. 22 rxb i uart receive data. 23 gpiob5/rtsb#/rs485b i/o general purpose i/o, or uart request-to-send output (active low), or auto rs-485 half- duplex control. defaults to gpio input with internal pull-up resistor. see automatic rts/cts hardware flow control on page 15 or multidrop mode with address matching on page 17 . 24 vio pwr i/o voltage input to the uart/gpio pins. must be between 1.8 and 3.6v. may be connected to vcc (pin 12) if vcc_reg input voltage is 5v. see usb power modes on page 11. 25 gnd pwr power supply common, ground. 26 gpiob4/ctsb# i/o general purpose i/o, or uart clear-to- send input (active low). defaults to gpio input with internal pull-up resistor. see automatic rts/cts hardware flow control on page 15 . 27 gpiob3/dtrb# i/o general purpose i/o, or uart data-ter minal-ready push-pull output (a ctive low). defaults to gpio input with intern al pull-up resistor. see automatic dtr/dsr hardware flow control on page 16 . 28 gpiob2/dsrb# i/o general purpose i/o, or uart data-set-r eady input (active low). defaults to gpio input with internal pull-up resistor. see automatic dtr/dsr hardware flow control on page 16 . 29 gpiob1/cdb# i/o general purpose i/o, or uart carrier-dete ct input (active low). defaults to gpio input with internal pull-up resistor. 30 gpiob0/rib#/rwkb# i/o general purpose i/o, or uart ring- indicator input (active low), or remote wakeup input. defaults to gpio input with internal pull-up resistor. see remote wakeup on page 9 . 31 gpioa0/ria#/rwka# i/o general purpose i/o, or uart ring- indicator input (active low), or remote wakeup input. defaults to gpio input with internal pull-up resistor. see remote wakeup on page 9 . 32 gpioa1/cda# i/o general purpose i/o, or uart carrier-detect input (active low). defaults to gpio input with internal pull-up resistor. 33 gpioa2/dsra# i/o general purpose i/o, or uart data-set-r eady input (active low). defaults to gpio input with internal pull-up resistor. see automatic dtr/dsr hardware flow control on page 16 . 34 gpioa3/dtra# i/o general purpose i/o, or uart data-ter minal-ready push-pull output (a ctive low). defaults to gpio input with intern al pull-up resistor. see automatic dtr/dsr hardware flow control on page 16 . 35 gpioa4/ctsa# i/o general purpose i/o, or uart clear-to- send input (active low). defaults to gpio input with internal pull-up resistor. see automatic rts/cts hardware flow control on page 15 . 36 gpioa5/rtsa#/rs485a i/o general purpose i/o, or uart request-to-send output (active low), or auto rs-485 half- duplex control. defaults to gpio input with internal pull-up resistor. see automatic rts/cts hardware flow control on page 15 or multidrop mode with address matching on page 17 . 37 rxa i uart receive data. pin no. pin name type description
? 2014 exar corporation xr21b1422 7 / 60 exar.com/xr21b1422 rev 1a type: i = input, o = output, i/o = input/output, pwr = power, od = open-drain 38 txa o uart transmit data. 39 gpioa6/clka i/o general purpose i/o, or clock or pulse output. defaults to gpio input with internal pull-up resistor. see programmable output clock on page 15 . 40 gpioa7/rs485a i/o general purpose i/o, or auto rs-485 half-d uplex control. defaults to gpio input with internal pull-up resistor. see multidrop mode with address matching on page 17 . pin no. pin name type description
? 2014 exar corporation xr21b1422 8 / 60 exar.com/xr21b1422 rev 1a functional block diagram usb slave interface 512-byte tx fifo gpios/ modem io txa internal oscillator (48mhz) usbd+ usbd- 512-byte rx fifo gpioa9/rxta gpioa8/txta gpioa7/xena gpioa6/clka gpioa5/rtsa#/xena gpioa4/ctsa# gpioa3/dtra# gpioa2/dsra# gpioa1/cda# gpioa0/ria# uart ch a fractional brg internal status and control registers vcc_reg gnd otp usb descriptors ldo 3v3 vcc vbus_sense reset# rxa usb_stat1 usb_stat2 vio uart ch b (same as ch a) txb rxb gpiob[9-0]
? 2014 exar corporation xr21b1422 9 / 60 exar.com/xr21b1422 rev 1a functional description usb interface the usb interface of the xr21b1422 is compliant with the usb 2.0 full-speed specifications. the xr21b1422 uses the following set of parameters: ? 1 control endpoint ? endpoint 0 as outlined in the usb specifications ? 1 configuration is supported ? 1 interface for each uart channel ? bulk-in and bulk-out endpoints ? interrupt-in endpoint for notifications usb vendor and product ids exars usb vendor id is 0x04e2. this is the default vendor id that is used for the xr21b1422. customers may obtain their own vendor id from usb.org. the default usb product id for the xr21b1422 is 0x1422. upon request, exar will provide up to 8 pid values for use with exars vid. the vid and pid can be changed using the vid and pid fields. refer to ta bl e 1 . usb suspend all usb peripheral devices must support the usb suspend mode. per usb standard, the xr 21b1422 device will begin to enter the suspend state if it does not detect any activity, (including start of frame or sof packets) on its usb data lines for 3 ms. the peripheral device must then reduce power consumption from vbus power within the next 7 ms to the allowed limit of 2.5 ma for the suspended state. note that in this context, the "device" is all circuitry (including the xr21b1422) tha t draws power from the host vbus. remote wakeup if the xr21b1422 device has been placed into the suspend stat e by the usb host, a high to low transition on the ri#/rwk# pins can be used to request that the host exit the suspende d state. by default the xr21b1422 device reports in its usb device attributes that it supports remote wakeup. the ri#/rwk# pins of each uart channel are enabled for remote wakeup signaling if their default configuration as an input pin has not been changed. the ri#/rwk# pins from each uart channel are logically anded, such that a logic 0 on any of the two pins will prev ent the remote wakeup signaling. addition- ally, the rx pins of each uart channel may also be enabled via otp to support remote wakeup. again all rx pins that are enabled to support remote wakeup signaling are also logicall y anded. note that the cdc driver does not support remote wakeup. usb strings usb specifies three character string descriptors that are provided to the usb host during enumeration in string descriptors: the manufacturer, product and serial strings. the default manufacturer and product strings for the xr21b1422 device are "exar corp." and, "exar usb uart", respectively. the serial number string is a unique alpha-numeric string programmed into the device at the factory. all character strings use unicode utf-16le format by default, but the unicode language id may be changed for the manufacturer and product strings. the defa ult character string language id is us english. if the lan- guage id is modified via otp, the serial number string should also be modified accordingly. to ensure unique serial number strings, it is recommended that the factory pre-programmed serial number string be used.
? 2014 exar corporation xr21b1422 10 / 60 exar.com/xr21b1422 rev 1a device driver the xr21b1422 device may be used with either a standard cdc-acm driver or an exar supplied custom driver. the cdc- acm driver is native to the operating system. in linux, t he cdc-acm driver will automatically load for the xr21b1422, but in the windows os, an extra inf file is required to install the cdc-acm driver. the custom drivers must also be installed, although for windows 7 os and newer with internet access and windows updates set to automatic, the latest windows- certified (whql/hck) driver will be do wnloaded and installed automatically. cdc-acm driver because the cdc-acm driver has no ability to access the xr21b142 2 internal device registers, the device is initialized to certain hardware defaults. by default the xr21b1422 enables ha rdware rts/cts flow control, gpio7 is set as active high auto rs-485 half-duplex control, and ri, cd and dsr pins are enabled to be interrupt sensitive. these settings are listed in ta bl e 2 . additionally, the low latency threshold in cdc mode is automatically set to 40,960 bps. refer to rx fifo low latency on page 14 . this threshold may be modified in the otp cdc_acm_baud_thresh locations. custom exar driver custom windows and linux drivers are available from exar. the custom driver allows software applications to make full use of the xr21b1422 register set and features. note that a custom driver must always immediately set custom_driver bit-0 = 1. once custom_driver bit-0 is set, the custom driver can use standard cdc-ac m commands without the xr 21b1422 automatically chan ging to the settings in the ta b l e 2 . table 1: usb string descriptor defaults descriptor value exar usb vendor id 0x04e2 exar usb product id 0x1422 manufacturer string exar corp. product string exar usb uart table 2: xr21b1422 register defaults with cdc-acm driver register value notes flow_control 0x0001 hardware flow control gpio_mode 0x0339 rts / cts flow control, gpio7 is used as rs-485 half-duplex enable (rs485) with active high polarity. gpio6 is a gpio input, rxt and txt remain enabled. gpio_direction 0x0028 dtr / rts are configured as outputs (txt, rxt, clk and rs485 are also spe- cial function outputs). all other gpios are configured as inputs. gpio_int_mask 0x03f0 ri, cd and dsr are interrupt sensitive, i.e. can cause a usb interrupt to be generated.
? 2014 exar corporation xr21b1422 11 / 60 exar.com/xr21b1422 rev 1a usb power modes the xr21b1422 device may be configured in any of the following power modes: bus-powered, self-powered 5v, or self- powered 3.3v. in all three modes, the vbus power signal from the usb host must be connected to the vbus_sense pin of the device. the default power mode for the xr21b1422 is bus powered. in this mode, the usb devices maximum power requirement from the host must be specified. in th is context, the usb device includes all components on the pcb that will draw power from the usb host vbus power. the default maximum power for the xr21b1422 is 100ma. this may be changed using the attributes field in the otp. bus-powered in bus-powered mode, vbus from the usb cable supplies 5v to the xr21b1422 device. the vcc pin will supply a 3.3v output. the vio pins may be externally connected to vcc or to an alternate voltage source. figure 1: bus-powered mode self-powered 5v in self-powered 5v mode, a local source provides 5v to the xr21b1422 device. the usb attributes should be changed in the otp to correctly report self-powered mode. the vcc pin will supply a 3.3v output. vio pins may be externally con- nected to vcc or to an alternate voltage source. figure 2: self-powered 5v mode vcc_reg vbus_sense xr21b1422 dp dm gnd vcc vbus dp dm gnd usb connector vio vcc_reg vbus_sense xr21b1422 dp dm gnd vcc vbus dp dm gnd usb connector vio 5v supply
? 2014 exar corporation xr21b1422 12 / 60 exar.com/xr21b1422 rev 1a self-powered 3.3v in self-powered 3.3v mode, a local source provides 3.3v to both the vcc_reg and vcc pins of the xr21b1422 device. the usb attributes should be changed in the otp to correctly report self-powered mode. vio pins may be externally con- nected to vcc or to an alternate voltage source. figure 3: self-powered 3.3v mode reset the xr21b1422 has three different types of resets: power-on reset or por, hardware reset, and usb bus reset. the results of each of the three types of resets are listed in ta bl e 3 . uart the uart may be configured via usb control transfers from the usb host. the uart transmitter and receiver sections are described separately in the following sections. at power-up, t he xr21b1422 will default to 115.2 kbps, 8 data bits, no parity bit, 1 stop bit, and no flow control. if a standard cdc driver accesses the xr21 b1422, these defaults will be changed. see device driver on page 10 . transmitter the transmitter consists of a 512-byte tx fifo and a transmit shift register (tsr). once a set transmit data interrupt out or bulk-out packet has been received and the crc has been validated, the data bytes in that packet are written into the tx fifo. data from the tx fifo is transfe rred to the tsr when the tsr is idle or has completed sending the previous data byte. the tsr shifts the data out onto the tx output pin at the selected baud rate. the transmitter sends the start bit fol- lowed by the data bits (starting with the lsb), inserts the proper parity-bit if enabled, and adds the stop-bit(s). the transmi t- ter may be configured for 5, 6, 7 or 8 data bits with or without parity or 9 data bits without parity. if 5, 6, 7 or 8 bit data with table 3: device resets reset type device actions power on reset (por) resets all registers and pins to default states including any otp modifications. locks otp from further writes if global lock is set. hardware reset resets all registers and pins to default states including any otp modifications. locks otp from further writes if global lock is set. usb bus reset resets usb interface, re-enumerate device, reset all internal states, clear uart fifos. does not reset registers or pin configurations. vcc_reg vbus_sense xr21b1422 dp dm gnd vcc vbus dp dm gnd usb connector vio 3.3v supply
? 2014 exar corporation xr21b1422 13 / 60 exar.com/xr21b1422 rev 1a parity is selected, the tx fifo contains 8 bits data and the parity bit is automatically generated and transmitted. if 9 bit da ta is selected, parity cannot be gene rated. the 9th bit will not be trans mitted unless the wide mode is enabled. wide mode transmit when both 9 bit data and wide mode are enabled, two bytes of data will be written into the tx fifo. the first byte is the first 8 bits (data bits 7-0) of the 9-bit data. bit-0 of the second byte is bit-8 of the 9-bit data. the data that is transmitted on the tx pin is as follows: start bit, 9-bit data, stop bit. wide mo de may be enabled using the tx_wide_mode and rx_wide_- mode registers. receiver the receiver consists of a 512-byte rx fifo and a receive shift register (rsr). data that is received in the rsr via the rx pin is transferred into the rx fifo. data from the rx fifo is sent to the usb host by in response to a bulk-in request. depending on the mode, error / status information for that data character may or may not be stored in the rx fifo with the data. normal receive operation with 5, 6, 7 or 8-bit data received data is stored in the rx fifo. any parity, framing or overrun error or break status information related to the data is discarded. the receive data format is shown in figure 4 . figure 4: receive data format normal receive operation with 9-bit data the first 8 bits of data received is stored in the rx fifo. the 9th bit as well as any parity, framing or overrun error or brea k status information related to the data is discarded. wide mode receive operation with 5, 6, 7 or 8-bit data two bytes of data are loaded into the rx fifo for each byte of data received. the first byte is the received data. the sec- ond byte consists of the error bits and break status. wide mode receive data format is shown in figure 5 . 1 st byte 7, 8, or 9 bit data 7 6 5 4 3 2 1 0 7 = ?0? in 7 bit mode
? 2014 exar corporation xr21b1422 14 / 60 exar.com/xr21b1422 rev 1a figure 5: wide mode receive data format wide mode receive operation with 9-bit data two bytes of data are loaded into the rx fifo for each byte of data received. the first byte is the first 8 bits of the receive d data. the 9th bit received is stored in the bit 0 of the second byte. the parity bit is not received / checked. the remainder o f the 2nd byte consists of the framing and overrun error bits and break status. error flags are also available from the error_status register and the interrupt packet, however these flags are historical flags indicating that an error has occurred since the previous request. therefore, no conclusion can be drawn as to which specific byte(s) may have contained an actual error. rx fifo low latency in normal operation all bulk-in transfers will be of maxpacketsize (64) bytes to im prove throughput and to minimize host pro- cessing. when there are 64 bytes of data in the rx fifo, t he xr21b1422 will acknowledge a bulk-in request from the host and transfer the data packet. if there are less than 64 bytes in the rx fifo, the xr21b1422 may respond to the bulk-in request with a nak indicating that data is not ready to transfer at that time. however, if there are less than 64 bytes in the rx fifo and no data has been received for more than 3 character times, the xr21b1422 will acknowledge the bulk-in request and transfer any data in the rx fifo to the usb host. in some cases, especially when the baud rate is low, this behavior may increase latency unacceptably. the xr21b1422 has a low latency register bit that will enable the xr21b1422 to immediately transfer any received data in the rx fifo to the usb host without waiting for 3 character times. the custom driver may be used to automatically set the rx_fi- fo_low_latency register to enable low latency mode, or the user may manually set it. with the cdc-acm driver, the low latency mode is automatically set whenever the baud rate is set to a value of less than 40960 bps using the cdc_ac- m_if_set_line_coding command. gpio each uart has 10 gpio pins in addition to the tx and rx pins. each gpio pin may also be configured for one or more special functions. all gpio pins as well as usb_stat1 and usb_stat2 may be configured for a variety of pin type options using the gpio_mode register or by writing the otp using xr_set_otp. all enabled pull-up and pull-down resistors are maintained during the usb suspend state. pin configurations set using xr_set_otp are enabled following the next 1 st byte 2 nd byte 5, 6, 7 or 8 bit mode 9 bit mode 7 6 5 4 3 2 1 0 x x x x o f b p x x x x o f b 8 7 6 5 4 3 2 1 0 1 st byte 2 nd byte 5, 6, and 7 = ?0? in 5, 6, or 7 bit mode p = parity error (=?0' if not enabled) b = break f = framing error o = overrun error x = ?0? b = break f = framing error o = overrun error x = ?0?
? 2014 exar corporation xr21b1422 15 / 60 exar.com/xr21b1422 rev 1a power-up reset and are permanent. during usb bus reset, resistors are disabled and are re-enabled after bus reset is de- asserted. pin configurations set us ing the gpio_mode register will be lost after por or usb bus reset. programmable output clock the gpio6/clk pin may be enabled as a clock output using the gpio_mode register. the outclk register can be used to program the output frequency of the clock from 24 mhz down to approximately 47 khz. the duty cycle can also be pro- grammed from 50/50 to a single low or high going pulse. the default values of zero for both div_hi and div_lo in the outclk register will result in a frequency of 24 mhz. for any non-zero values for div_hi and div_lo, the clock frequency is determined by the formula: freq = 24 mhz / (div_hi + div_lo). the duty cycle is determined by the ratio of div_hi to div_lo. flow control the xr21b1422 is able to perform both hardware and software flow control. both hardware and software flow control modes are configured via the gpio_mode and flow_control registers. in both modes, flow control is asserted when the bytes in the rx fifo reach the watermark set in the rx_threshold register. hardware flow control can either be rts/cts or dtr/dsr controlled. note that although the default pin configuration for gpio5/rts#/rs485 and gpio4/cts# are for rts output and cts input respectively, the hardware rts/cts flow control mode must be set in the flow_con trol register in order to utilize the flow control functionality. automatic rts/cts hardware flow control automatic rts flow control is used to prevent data overrun errors in the local rx fifo using the rts signal to the remote uart. the rts signal will be asserted (low) when there are less than 450 bytes in the re ceive fifo. when the rx fifo reaches the 450 byte threshold, the rts pin will be de-asserted. the cts# input is monitored by the remote uart to sus- pend/restart the local transmitter. refer to figure 6 . conversely, when the remote uart reaches its receive fifo threshold, its rts will be de-asserted, and the b1422 cts input will cause the devi ce to suspend data transmission.
? 2014 exar corporation xr21b1422 16 / 60 exar.com/xr21b1422 rev 1a figure 6: auto rts and cts flow control operation automatic dtr/dsr hardware flow control auto dtr/dsr hardware flow control behaves the same as the auto rts/cts hardware flow control described above except that it uses the dtr# and dsr# signals. gpio2 an d gpio3 become dsr# and dtr#, respectively, when the gpi- o_mode register is configured for dtr/dsr hardware flow control. automatic xon/xoff software flow control when software flow control is enabled, the xr21b1422 compares the receive data characters with the programmed xon or xoff characters. if the received character matches the progra mmed xoff character, the xr21b1422 will halt transmis- sion as soon as the current character has completed transm ission. data transmission is resumed when a received charac- ter matches the xon character. in the receive data direction, the xoff character will be sent when there are 450 bytes in the receive fifo. when there are again less than 450 bytes in the rx fifo, the xon character will be sent. this threshold may be changed using the rx_- threshold register. software flow control is enabled / disabled by the flow_control register. additionally, the xon_char and xoff_char registers may be used to configure the start (xon) and stop (xoff) characters. transmitter auto cts monitor receiver fifo trigger reached auto rts trigger level remote uart uartb rtsa# ctsb# txb rxa on on off on on off 1 2 3 4 1) com port opened, rx fifo empty, rtsa# output is asserted 2) signal propagated to ctsb# input 3) data bytes enter tx fifo, begin transmitting on txb 4) data propagates to receiving device rxa 5) rx fifo reaches threshold 6) rtsa# de-asserts 7) signal propagates to ctsb# input 8) transmission stops on txb 9) usb bulk-in empties rx fifo below threshold, rtsa# is asserted 10) signal propagated to ctsb# input 11) data bytes resume transmitting on txb 5 6 7 8 9 10 11 rtsa# ctsb# txb rxa ctsa# txa rtsb# rxb receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor local uart uarta
? 2014 exar corporation xr21b1422 17 / 60 exar.com/xr21b1422 rev 1a multidrop mode with address matching the xr21b1422 device has two address matching modes wh ich are set by the flow_control and gpio_mode regis- ters. these modes are intended for use in a multi-drop network application. address matching may be used with any size data character, as well as with and without parity. an address match occurs when the last (most significant) received data bit or the parity bit, if there is one, is a 1 and the address matches the value stored in either the xon_char or xoff_char register. to send an address byte use 5, 6, 7, 8 or 9 bit data with either the most significant data bit a 1 or if parity is used, set mark parity. to send data bytes, the most significant data bit must be a 0 or use space parity. receiver if an address match occurs in either of the address matching modes, the address byte and all subsequent data bytes will be loaded into the rx fifo. the uart receiver will automatically be disabled when an address by te is received that does not match the values in the xon_char or xoff_char characters. transmitter in flow control mode 3, the uart transmitter will transmit irresp ective of the rx address match. in flow control mode 4, the uart will only transmit following an rx address match. programmable turn-around delay by default, the selected rs-485 half- duplex enable pin (either gp io7/rs485 or gpio5/rts#/r s485) will be de-asserted immediately after the stop bit of the last byte has been shifted. however, this may not be ideal for systems where the signal needs to propagate over long cables. therefore, the de-assertion of the rs-485 half-duplex enable can be delayed from 1 to 15 bit times via the xcvr_en_delay register to allow for the data to reach distant uarts. uart half-duplex mode in uart half-duplex mode, the uart will ignore any data on the rx input when the uart is transmitting data. the half- duplex mode can be configured using the flow_control register. ir mode the xr21b1422 supports ir mode at a maximum baud rate of 2. 5 mbaud with transmit pulses of 3/16th or 4/16th of a bit period and centered in the bit period. receive data may be inverted to conform to some manufacturers non-standard devices. ir mode is disabled by default but may be enabled by the ir_mode register. usb_stat pins the xr21b1422 has two usb_stat output pins that may be used to indicate 3 different statuses in either positive or nega- tive polarity. the suspend status indicate s that the xr21b1422 device has been placed into a suspended state by the usb host. this output can then be used by external circuitry, for example, to power down devices in order to meet usb requirements for suspend mode. the low_power status is similar to the suspend status, but low_power is also asserted for high power devices (any device that consumes more than 100 ma of vbus power from the usb host), before the device is configured during enumeration by the usb host. for low power devices (devices that consume 100 ma or less of vbus power), suspend and low_power status outputs ar e functionally the same. lastly, the bus_reset output status is asserted any time the xr21b1422 device is being reset by the usb host. this status output could be used, for example, by an fpga or other logic device to synchronize this external logic with the xr21b1422 device. suspend mode settings the use_suspend bit controls the gpio pins when the xr21b 1422 device is suspended by the usb host. if use_sus- pend is cleared to 0, the gpio pins retain their output states when the device is suspended. when use_suspend is set to 1, the gpio pins behavior is defined by the suspend_state and suspen d_mode registers, with the following exceptions: gpio0/clk when configured as an output clock will always be driven low, i. e the clock output will stop, and gpio1/rts#/rs485 or gpio3/rs485 when configured as auto. rs-485 half-dup lex enable will always be de-asserted.
? 2014 exar corporation xr21b1422 18 / 60 exar.com/xr21b1422 rev 1a note that use_suspend does not affect the uart rx and tx pins. during suspend state, rx and tx will always idle to a logic 1 state. the suspend_state field will set or clea r the gpio pins and the suspend_mode field will configure gpio outputs as either open drain or push -pull outputs. suspend_state and suspend_mode may be configured through registers or otp. as opposed to otp configuration, register configurations are not retained if the power is lost or the bus is reset. txt and rxt pins the transmit toggle and receive toggle pins "toggle" at a rate of approximately 10 hz whenever the uart transmit and receive pins (respectively) are active. otp the otp is an on-chip non-volatile memory, that is incremental ly one-time programmable via the usb interface. some bits are pre-programmed at the factory and caution must be taken not to program any locations except those user defined addresses given in this data sheet. once a specific portion of the otp is programmed, the prog bit for that section of the otp must be set and further changes to that section will not be allowed.
? 2014 exar corporation xr21b1422 19 / 60 exar.com/xr21b1422 rev 1a usb control commands the following table shows all of the usb control commands that are supported by the xr21b1422. commands include standard usb commands, cdc-acm commands and exar vendor s pecific commands. the device internal registers are accessed using the vendor specific xr_get_reg and xr_set_reg, xr_get_revision, xr_get_usb_stat and xr_set_usb_stat vendor specific commands. table 4: supported usb control commands name request type request value index length description lsb msb lsb msb lsb msb dev get_status 0x80 0x0 0x0 0x0 0x0 0x0 0x2 0x0 device: remote wake-up + self- powered if get_status 0x81 0x0 0x0 0x0 0x0 0x0 0x2 0x0 interface: zero ep get_status 0x82 0x0 0x0 0x0 0x0,0x4, 0x84 0x0 0x2 0x0 endpoint: halted dev clear_feature 0x00 0x1 0x1 0x0 0x0 0x0 0x0 0x0 device remote wake-up ep clear_feature 0x02 0x1 0x0 0x0 0x0,0x4, 0x84 0x0 0x0 0x0 endpoint halt dev set_feature 0x00 0x3 0x1 0x0 0x0 0x0 0x0 0x0 device remote wake-up ep set_feature 0x02 0x3 0x0 0x0 0x0,0x4, 0x84 0x0 0x0 0x0 endpoint halt set_address 0x00 0x5 addr 0x0 0x0 0x0 0x0 0x0 addr = 1 to 127 get_descriptor 0x80 0x6 0x0 0x1 0x0 0x0 len msb len msb device descriptor get_descriptor 0x80 0x6 0x0 0x2 langid langid len msb len msb configuration descriptor get_descriptor 0x80 0x6 0x0 0x3 0x0 0x0 len msb len msb string descriptor get_configuration 0x80 0x8 0x0 0x0 0x0 0x0 0x1 0x0 set_configuration 0x00 0x9 n 0x0 0x0 0x0 0x0 0x0 n = 0, 1 get_interface 0x81 0x10 0x0 0x0 0x0 0x0 0x1 0x0 cdc_acm_if set_line_coding 0x21 0x20 0x0 0x0 chan # 0x0 0x7 0x0 set the uart baud rate, parity, stop bits, etc. channel #0, 2 for channel a, b respectively. cdc_acm_if get_line_coding 0xa1 0x21 0x0 0x0 chan # 0x0 0x7 0x0 get the uart baud rate, parity, stop bits, etc. channel #0, 2 for channel a, b respectively. cdc_acm_if set_control_ line_state 0x21 0x22 0x0 0x0 chan # 0x0 0x7 0x0 set/clear dtr in cdc-acm mode. channel #0, 2 for chan- nel a, b respectively. cdc_acm_if send_break 0x21 0x23 val lsb val msb chan # 0x0 0x0 0x0 send a break for the specified duration. channel #0, 2 for channel a, b respectively. xr_get_chip_id 0xc0 0xff 0x0 0x0 0x0 0x0 0x6 0x0 get exar vid (2 bytes), pid (2 bytes) and bcddevice (2 bytes)
? 2014 exar corporation xr21b1422 20 / 60 exar.com/xr21b1422 rev 1a xr_set_reg see ta b l e 5 0x41 0x0 write- data lsb write- data msb write addr chan # 0x0 0x0 vendor specific register access. channel #0, 2 for channel a, b respectively. xr_get_reg see ta b l e 5 0xc1 0x0 0x0 0x0 read addr chan # 0x2 0x0 vendor specific register access. channel #0, 2 for channel a, b respectively. xr_get_revision see ta b l e 5 0xc0 0x0 0x0 0x0 0x60 0x02 0x2 0x0 vendor specific register access. xr_set_usb_stat see ta b l e 5 0x40 0x0 write- data lsb write- data msb 0x62 0x02 0x0 0x0 vendor specific register access. xr_set_usb_stat see ta b l e 5 0xc0 0x0 0x0 0x0 0x62 0x02 0x2 0x0 vendor specific register access. table 4: supported usb control commands name request type request value index length description lsb msb lsb msb lsb msb
? 2014 exar corporation xr21b1422 21 / 60 exar.com/xr21b1422 rev 1a register set description the internal register set of the xr21b1422 controls the uart channel functionality, basic functionality of the fifos, otp controls, as well as registers associated with the processing of driver commands. all registers are accessible via the usb interface using the xr_set_reg and xr_get_reg usb commands, except for the revision_id and usb_stat reg- isters which are accessible with the xr_get_revision an d xr_get/set_usb_stat commands respectively. note that the uart_enable register should be used to disable the uart prior to any register write and re-enable the uart follow- ing any single or sequence of register writes except for the gpio_set, gpio_clear, tx_break and error_status registers. all registers are 16 bits wide. the upper byte of single byte registers as well as bit locations with field label of 0 in ta b l e 5 are reserved. all reserved bits must be written as zeroes when modifying register contents. table 5: xr21b1422 register map address register name bit 7 (15) bit 6 (14) bit 5 (13) bit 4 (12) bit 3 (11) bit 2 (10) bit 1 (9) bit 0 (8) 0x000 uart_enable 0 0 0 0 0 0 rx tx 0x006 flow_control 0 0 0 0 half- duplex flow control mode select 0x007 xon_char value 0x008 xoff_char value 0x009 error_status break status overrun error parity error framing error break error 000 0x00a tx_break[15:8] value (msb) tx_break[7:0] value (lsb) 0x00b xcvr_en_delay 0 0 0 0 delay 0x00c gpio_mode[15:8] 0 0 0 0 rxt_en txt_en gpio_mode[7:0] clk_en rs485_sel xcvr enable pin xcvr enable polarity mode select 0x00d gpio_direction[15:8] 0 0 0 0 0 0 gpio9 gpio8 gpio_direction[7:0] gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x00e gpio_set[15:8] 0 0 0 0 0 0 gpio9 gpio8 gpio_set[7:0] gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x00f gpio_clear[15:8] 0 0 0 0 0 0 gpio9 gpio8 gpio_clear[7:0] gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x010 gpio_state[15:8] 0 0 0 0 tx rx gpio9 gpio8 gpio_state[7:0] gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x011 gpio_int_mask[15:8] 0 0 0 0 0 rx gpio9 gpio8 gpio_int_mask[7:0] gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x012 customized_int 0 0 0 0 0 0 int_ break_ neg en
? 2014 exar corporation xr21b1422 22 / 60 exar.com/xr21b1422 rev 1a 0x013 pin_open_drain[15:8] 0 0 0 0 tx 0 gpio9 gpio8 pin_open_drain[7:0] gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x014 pin_pullup_en[15:8] 0 0 0 0 0 rx gpio9 gpio8 pin_pullup_en[7:0] gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x015 pin_pulldown_en[15:8] 0 0 0 0 0 rx gpio9 gpio8 pin_pulldown_en[7:0] gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x016 loopback 0 0 0 0 0 dtr_ dsr rts_ cts tx_ rx 0x017 ir_mode 0 0 0 0 0 tx_ pulse rx_ invert en 0x018 outclk[15:8] div_hi outclk[7:0] div_lo 0x01f remote_wake 0 0 0 0 rx_en ri_en 0 0 0x040 tx_fifo_flush 0 0 0 0 0 auto_- close auto_ open reset 0x041 tx_fifo_count[15:8] 0 0 0 0 0 0 count[9:8] tx_fifo_count[7:0] count[7:0] 0x042 tx_wide_mode 0 0 0 0 0 0 0 en 0x043 rx_fifo_flush 0 0 0 0 0 auto_ close auto_ open reset 0x044 rx_fifo_count[15:8] 0 0 0 0 0 0 count[9:8] rx_fifo_count[7:0] count[7:0] 0x045 rx_wide_mode 0 0 0 0 0 0 0 en 0x046 low_latency 0 0 0 0 0 0 0 en 0x047 rx_threshold[15:8] 0 0 0 0 0 0 count[9:8] rx_threshold[7:0] count[7:0] 0x060 custom_driver 0 0 0 0 0 0 0 active 0x06a suspend_state[15:8] 0 0 dsr dtr ri cd 0 0 suspend_state[7:0] rxt txt 0 0 rs485 cts rts clk 0x06b suspend_mode[15:8] use_ sus- pend 0dsrdtrri cd 0 0 suspend_mode[7:0] rxt txt 0 0 rs485 cts rts clk 0x260 revision_id a value table 5: xr21b1422 register map address register name bit 7 (15) bit 6 (14) bit 5 (13) bit 4 (12) bit 3 (11) bit 2 (10) bit 1 (9) bit 0 (8)
? 2014 exar corporation xr21b1422 23 / 60 exar.com/xr21b1422 rev 1a 0x262 usb_status[15:8] b 00state1 sel1 ctrl1 usb_status[7:0] 0 0 state0 sel0 ctrl0 a. the revision_id register is accessed using xr_g et_revision, i.e. not xr_ set_reg or xr_get_reg. b. the usb_status registers are accessed using xr_set_usb_stat and xr_get_usb_stat, i.e. not xr_set_reg or xr_get_reg. table 5: xr21b1422 register map address register name bit 7 (15) bit 6 (14) bit 5 (13) bit 4 (12) bit 3 (11) bit 2 (10) bit 1 (9) bit 0 (8)
? 2014 exar corporation xr21b1422 24 / 60 exar.com/xr21b1422 rev 1a xr21b1422 register descriptions uart_enable (0x000) - read/write the uart transmitter and receiver must be disabled before writing to any other uart registers except for the gpio_set, gpio_clear, tx_break and error_status registers. flow_control (0x006) - read/write this register selects the flow control mode. this register should only be written to when the uart is disabled. writing to the flow_control register when the uart is enabled will result in undefined behavior. xon_char (0x007) - read/write the xon_char stores the 5 through 8 bit xon character that is used for automatic software flow control. in 9 bit mode, only bits 7 through 0 are used, i.e. bit 8 is always a 0. alternately, this register holds the unicast address for multi-drop appli- cations with address matching mode. bit default description 15:2 0 reserved these bits are reserved and should be written as 0. 10 enable uart rx 0: uart rx disabled 1: uart rx enabled 00 enable uart tx 0: uart tx disabled 1: uart tx enabled bit default description 15:4 0 reserved these bits are reserved and should be written as 0. 30 uart half-duplex mode 0: normal (full-duplex) mode. the uart can transmit and receive data at the same time. 1: uart half-duplex mode. in half-duplex mode, any data on the rx pin is ignored when the uart is transmitting data. 2:0 000 mode 000: mode 0. no flow control, no address matching. 001: mode 1. hw flow control enabled. auto rts/cts or dtr/dsr must be selected by gpio_mode. 010: mode 2. sw flow control enabled. 011: mode 3. multidrop mode - rx only after address ma tch, tx independent. (typically used with gpio_mode 3). 100: mode 4. multidrop mode - rx/tx only after address match. (typically used with gpio_mode 4). 101 to 111 : re s e r ve d bit default description 15:8 0 reserved these bits are reserved and should be written as 0.
? 2014 exar corporation xr21b1422 25 / 60 exar.com/xr21b1422 rev 1a xoff_char (0x008) - read/write the xoff_char stores the 5 through 8 bit xoff character that is used for automatic software flow control. in 9 bit mode, only bits 7 through 0 are used, i.e. bit 8 is always a 0. alternately, this register holds the multicast address for multi-dr op applications with address matching mode. error_status (0x009) - read-clear this register reports any historical framing, parity and overrun errors as well as both current and historical break status, since the last time this register was read. as such, it does not indicate which character(s) the error(s) were associated with. for diagnostic purposes, wide_mode may be enabled such that errors are directly associated with the current byte. 7:0 0x11 xon character in automatic software flow control mode, the uart wi ll suspend data transmission when the xon character has been received. for behavior in the address match mode, see multidrop mode with address matching on page 17 . bit default description 15:8 0 reserved these bits are reserved and should be written as 0. 7:0 0x13 xoff character in automatic software flow control mode, the uart will suspend data transmission when the xoff character has been received. for behavior in the address match mode, see multidrop mode with address matching on page 17 . bit default description 15:8 0 reserved these bits are reserved and should be written as 0. 70 break status (read-only) 0: break condition is not present. 1: break condition is currently being detected. 60 overrun error 0: no overrun error. 1: an overrun error has been detected (clears after read). an ov errun error occurs when the rx fifo is full and another byte of data is received. 50 parity error 0: no parity error. 1: a parity error has been detected (clears after read). 40 framing error 0: no framing error. 1: a framing error has been detected (clears after read). a fr aming error occurs when a stop bit is not present when it is expected. 30 break error 0: no break condition. 1: a break condition has been detected (clears after read). 2:0 0 reserved these bits are reserved and should be written as 0. bit default description
? 2014 exar corporation xr21b1422 26 / 60 exar.com/xr21b1422 rev 1a tx_break (0x00a) - read/write this register controls uart tx break signaling. xcvr_en_delay (0x00b) - read/write gpio_mode (0x00c) - read/write bit default description 15:0 0 value for value tx_break value of n: if n == 0xffff, the uart tx outputs a continuous break signal. if 0x0000 < n < 0xffff (a maximum of 64,534 ms), the uart tx outputs a break signal that lasts n ms, and the register serves as a counter, count- ing down to 0, decrementing by 1 every millisecond. if n == 0x0000, the uart tx stops sending the break signal. when the user writes to this register, any previous proces s is terminated, and the new command takes effect. if data is being shifted out of the tx pin, the data will be completely shifted out before the break condition is generated. note: after this register is programmed from 0x0000 to a non-zero value, the uart tx may take up to, but no more than 1 ms, before sending out the break condition. in addition, after the break counter decrements to zero, the uart tx may take up to, but no more than 2 uart characters, based on the current uart configuration, before stopping the break. thus, the actual break length may be slightly longer than the programmed va lue, by up to, but no more than (1ms + 2x uart-character- length). bit default description 15:4 0 reserved these bits are reserved and should be written as 0. 3:0 0 turn-around delay turn-around delay controls the number of bit times (0-15) to wait before changing the direction of the rs-485 half-duplex from transmit to receive when auto rs-485 half-duplex control is enabled. this allows for propagation of characters to complete across lengthy mediums. bit default description 15:10 0 reserved these bits are reserved and should be written as 0. 91 receive toggle 0: gpio9 is used for general purpose i/o 1: gpio9 is used to receive toggle output (default). 81 transmit toggle 0: gpio8 is used for general purpose i/o. 1: gpio8 is used to transmit toggle output (default). 70 clock enable 0: gpio6 is used for general purpose i/o 1: gpio6 is used to output a clock. see outclk (0x018) - read/write on page 33 .
? 2014 exar corporation xr21b1422 27 / 60 exar.com/xr21b1422 rev 1a gpio_direction (0x00d) - read/write this register controls the direction of pins that are configur ed as gpio. pins that are confi gured for alternate functions via the gpio_mode register are not controlled by this register. gpio_set (0x00e) - write-only this register controls pins configured as gpio outputs. pins configured for alternate functions via the gpio_mode register are not controlled by this register. writing a 1 to a bit positi on in this register sets the corresponding gpio output high. writ- ing a 0 to a bit has no effect. for gpio pins configured as inputs via the gpio_direction register, this register has no effect. 6:5 0 auto rs-485 half-duplex select 00: gpio. gpio7/rs485 is used for general purpose i/o 01: rs485_en_act. gpio7/rs485 is used for auto rs-485 half- duplex enable. asserted whenever the uart is transmitting 10: rs485_en_flow. gpio7/rs485 is used for auto rs-485 half- duplex enable. asserted for the duration of the address match 11: reserved. reserved value, do not use 40 auto rs-485 half-duplex pin 0: gpio5/rts#/rs485 function is selected by gpio_mode[2:0]. gpio7/rs485 function is gpio. 1: gpio7/rs485 function is selected by gpio_mode[6:5]. gp io5/rts#/rs485 function must be any function other than that selected for gpio7/rs485. 30 auto rs-485 half-duplex polarity 0: active low auto. rs-485 half-duplex enable 1: active high auto. rs-485 half-duplex enable 2:0 000 gpio mode select 000: gpio. rts/cts and dtr/dsr are used for general purpose i/o. 001: rts_cts. gpio4 and gpio5 used for auto rts/cts hw flow control 010: dtr_dsr. gpio2 and gpio3 used for auto dtr/dsr hw flow control 011: rs485_en_act. gpio5/rts#/rs485 pin used fo r auto .rs-485 half-duplex enable during transmit 100: rs485_en_flow. gpio5/rts#/rs485 pin used for auto rs-485 half-duplex enable after address match. 101 to 111: reserved. reserved value, do not use. bit default description 15:10 0 reserved these bits are reserved and should be 0. 9:0 0 gpio direction of gpio[9:0] 0: gpiox is an input. 1: gpiox is an output. bit default description 15:10 0 reserved these bits are reserved and should be 0. 9:0 0 gpio set of gpio[9:0] 0: no effect on gpiox pin. 1: gpiox output is set to a 1. bit default description
? 2014 exar corporation xr21b1422 28 / 60 exar.com/xr21b1422 rev 1a gpio_clear (0x00f) - write-only this register controls pins configured as gpio outputs. pins configured for alternate functions via the gpio_mode register are not controlled by this register. writing a 1 to a bit position in this register clears the corresponding gpio output low. writing a 0 to a bit has no effect. for gpio pins configured as inputs via the gpio_direction register, this register has no effect. gpio_state (0x010) - read/write gpio_int_mask (0x011) - read/write this register is used to configure whether a change in pin state causes the device to generate a usb interrupt packet. note that the gpio status register will still report the gpio pin state when read, and if an interrupt packet is formed due to other interrupt trigger, the interrupt packet will contain the current stat e of the pin. this register applies to all inputs pins irr espec- tive of if they are configured as gpio or alternate functions. bit default description 15:10 0 reserved these bits are reserved and should be 0. 9:0 0 gpio set of gpio[9:0] 0: no effect on gpiox pin. 1: gpiox output is cleared to a 0. bit default description 15:10 0 reserved these bits are reserved and should be 0. 9:0 0 gpio state of gpio[9:0] read returns state of all pins, whether gp io or alternate function, input or output 0: write clears the respective gpio output to a 0 1: write sets the respective gpio output to a 1 bit default description 15:10 0 reserved these bits are reserved and should be written as 0. 9:0 0x100 gpio interrupt mask of gpio[9:0] 0: a change in the input pin's state causes the device to generate an interrupt packet 1: a change in the input pin's state does not cause the device to generate an interrupt packet
? 2014 exar corporation xr21b1422 29 / 60 exar.com/xr21b1422 rev 1a customized_int (0x012) - read/write this register enables the customized inte rrupt packet format that will report all gp io pin status in the interrupt packet. bit default description 15:2 0 reserved these bits are reserved and should be written as 0. 10 break interrupt enable 0: no interrupt is generated when break character is received. 1: interrupt is generated when break character is received. 00 enable 0: use standard interrupt packet. see ta b l e 6 . 1: use customized interrupt packet. see ta b l e 8 . table 6: standard interrupt packet format offset field size (bytes) value description 0 bmrequesttype 1 8b10100001 d7 = device-to-host direction d6:5 = class type d4:0 = interface recipient 1 bnotification 1 8h20 defined encoding for serial_state 2 wvalue 2 16h0000 4 windex 2 16h0000 d15:8 = reserved (0) d7:0 = interface number, 8h00 for the cdc command interface 6 wlength 2 16h0002 2 bytes of transferred data 8 data 2 standard int_status see ta b l e 7 d15-7 = reserved (0) d6 = boverrun d5 = bparity d4 = bframing d3 = bringsignal (ri) d2 = bbreak d1 = btxcarrier (dsr) d0 = brxcarrier (cd)
? 2014 exar corporation xr21b1422 30 / 60 exar.com/xr21b1422 rev 1a if the exar vendor specific packet mapping is enabled then the interrupt packet format is as shown in ta b l e 8 . pin_open_drain (0x013) - read/write this register controls all pins configured as outputs irrespective of if they are configured as gpio or alternate functions. table 7: data field of standard interrupt packet bit field description d15:7 reserved (future use) d6 boverrun received data has been discarded due to overrun in the device. d5 bparity a parity error has occurred. d4 bframing a framing error has occurred. d3 bringsignal state of ring signal detection of the device. d2 bbreak state of break detection mechanism of the device. d1 btxcarrier state of transmission carrier. this signal corresponds to v.24 signal 106 and rs-232 signal dsr. d0 brxcarrier state of receiver carrier detection mechanism of device. this signal corresponds to v.24 signal 109 and rs-232 signal dcd. table 8: customized interrupt packet format offset field size (bytes) value description 0 gpio_state 2 byte 0: gpio_state[7:0] byte 1: gpio_state[9:8] 2 gpio_int 2 byte 2: gpio_int[7:0] byte 3: gpio_int[9:8] 4 data 1 d15:4 = reserved (0) d3 = overrun error d2 = parity error d1 = frame error d0 = break status bit default description 15:12 0 reserved these bits are reserved and should be written as 0. 11 0 uart tx 0: tx pin is push-pull output 1: tx pin pin is open drain output 10 0 reserved these bits are reserved and should be written as 0.
? 2014 exar corporation xr21b1422 31 / 60 exar.com/xr21b1422 rev 1a pin_pullup_en (0x014) - read/write this register controls all pins configured as inputs irrespective of if they are configured as gpio or alternate functions. pin_pulldown_en (0x015) - read/write this register controls all pins configured as inputs irrespective of if they are configured as gpio or alternate functions. 9:8 0 pin open drain on gpio[9:8] 0: pin configured as output is push-pull output 1: pin configured as output is open drain output 71 pin open drain on gpio7/rs485 0: pin configured as output is push-pull output 1: pin configured as output is open drain output 6:0 0 pin open drain on gpio[6:0] 0: pin configured as output is push-pull output 1: pin configured as output is open drain output bit default description 15:11 0 reserved these bits are reserved and should be written as 0. 10 1 rx 0: disable pull-up on the rx pin 1: enable pull-up on the rx pin. if bot h pull-up and pull-down resistors are se lected, only the pull-up will be enabled. 9:0 1 pin pull-up enable on gpio[9:0] 0: disable pull-up on the corresponding input pin 1: enable pull-up on the corresponding input pin. if both pull-up and pull-down resistors are selected for a given gpio, only the pull-up will be enabled. bit default description 15:11 0 reserved these bits are reserved and should be written as 0. 10 0 rx 0: disable pull-down on the rx pin 1: enable pull-down on the rx pin. if both pull-up and pul l-down resistors are selected, only the pull-up will be enabled. 9:0 0 pin pull-down enable on gpio[9:0] 0: disable pull-down on the corresponding input pin 1: enable pull-down on the corresponding input pin. if both pul l-up and pull-down resistors are selected for a given gpio, only the pull-up will be enabled. bit default description
? 2014 exar corporation xr21b1422 32 / 60 exar.com/xr21b1422 rev 1a loopback (0x016) - read/write this register is used to configure the internal uart loopback. ir_mode (0x017) - read/write bit default description 15:3 0 reserved these bits are reserved and should be written as 0. 20 dtr_dsr when this bit is set, dtr is looped back to dsr. 0: disable loopback. 1: enable loopback. 10 rts_cts when this bit is set, rts is looped back to cts. 0: disable loopback. 1: enable loopback. 00 tx_rx when this bit is set, all transmitted uart data is internally l ooped back to the uart receiver. note that when internal loop- back is enabled, external tx data will be disabled and rx data will be ignored. 0: disable loopback. 1: enable loopback. bit default description 15:3 0 reserved these bits are reserved and should be written as 0. 20 tx_pulse this bit controls the pulse width of the tx data 0: tx pulse width is 3/16th of the bit period 1: tx pulse width is 4/16th of the bit period 10 rx_invert this bit inverts the rx data for ir devices that do not conform to standard. 0: rx data is not inverted 1: rx data is inverted 00 en this register bit is used to enable the infrared (ir) mode. 0: disable ir mode. 1: enable ir mode.
? 2014 exar corporation xr21b1422 33 / 60 exar.com/xr21b1422 rev 1a outclk (0x018) - read/write this register is used to set the output clock frequency and duty cycle. remote_wake (0x01f) - read/write this register is used to configure the remote wakeup feature. tx_fifo_flush (0x040) - write only this register is used to flush the transmit fifo. bit default description 15:8 0 div_hi sets the high period of the clock in intervals of 41.67 ns. 7:0 0 div_lo sets the low period of the clock in intervals of 41.67 ns. bit default description 15:4 0 reserved these bits are reserved and should be written as 0. 30 rx_en 0: the xr21b1422 device is not sensitive to rx pin for remote wakeup 1: a high to low transition on the rx pin signals a remote wak eup event to the xr21b1422 device if the rx pin is configured as an input. 21 ri_en 0: the xr21b1422 device is not sensitive to the ri#/rwk# pin for remote wakeup. 1: a high to low transition on the ri#/rwk# pin signals a remo te wakeup event to the xr21b1422 device if the ri#/rwk# pin is configured as an input. 1:0 0 reserved these bits are reserved and should be written as 0. bit default description 15:3 0 reserved these bits are reserved and should be written as 0. 20 auto_close 0: no effect on the tx fifo when the uart port tx is disabled 1: the tx fifo is automatically flushed when the uart port tx is disabled 11 auto_open 0: no effect on the tx fifo when the uart port tx is enabled 1: the tx fifo is automatically flushed when the uart port tx is enabled 00 reset 0: no effect on the tx fifo 0: resets the tx fifo, self-clearing
? 2014 exar corporation xr21b1422 34 / 60 exar.com/xr21b1422 rev 1a tx_fifo_count (0x041) - read only this register is used to read the number of bytes currently in the transmit fifo. tx_wide_mode (0x042) - read/write this register is used to enable the wide mode for the transmitter. rx_fifo_flush (0x043) - write only this register is used to flush the receive fifo. rx_fifo_count (0x044) - read only this register is used to read the number of bytes currently in the receive fifo. bit default description 15:10 0 reserved these bits are reserved and should be written as 0. 9:0 0 count reports the number of bytes currently in the tx fifo. bit default description 15:1 0 reserved these bits are reserved and should be written as 0. 00 enable 0: normal (5, 6, 7, 8 or 9 bit data) mode 1: wide mode bit default description 15:3 0 reserved these bits are reserved and should be written as 0. 20 auto_close 0: no effect on the rx fifo when the uart port rx is disabled 1: the rx fifo is automatically flushed when the uart port rx is disabled 11 auto_open 0: no effect on the rx fifo when the uart port rx is enabled 1: the rx fifo is automatically flushed when the uart port rx is enabled 00 reset 0: no effect on the rx fifo 1: resets the rx fifo, self-clearing bit default description 15:10 0 reserved these bits are reserved and should be written as 0.
? 2014 exar corporation xr21b1422 35 / 60 exar.com/xr21b1422 rev 1a rx_wide_mode (0x045) - read/write this register is used to enable the wide mode for the receiver. low_latency (0x046) - read/write this register is automatically set to logic 1 for baud rates below 40,960 bps when using the cdc-acm driver. a custom driver can also automatically enable low latency mode based upon the selected baud or the user may manually enable it by writing to this register. rx_threshold (0x047) - read/write this register sets the threshold for asserting flow control when enabled in the uart. this register applies to both hardware and software flow control. 9:0 0 count reports the number of bytes currently in the rx fifo. bit default description 15:1 0 reserved these bits are reserved and should be written as 0. 00 en 0: normal (5, 6, 7, 8 or 9 bit data) mode 1: wide mode. see wide mode transmit on page 13 , wide mode receive operation with 5, 6, 7 or 8-bit data on page 13 and wide mode receive operation with 9-bit data on page 14 . bit default description 15:1 0 reserved these bits are reserved and should be written as 0. 00 en 0: data from the rx fifo is not immediately forwarded to the usb host following the bulk-in request until bmaxpacketsize (normally 64 bytes) bytes have been received or a timeout per iod (of 3 character times) has been reached. (note: when the cdc-acm driver is used, bmaxpacketsize is 63 bytes.) 1: receive data is forwarded from rx fifo immediately following the bulk-in request. bit default description 15:10 0 reserved these bits are reserved and should be written as 0. 9:0 0x1c2 count hardware or software flow control is asserted when the rx_fif o reaches the threshold count set in this register. default value for this register is 450 or 0x1c2. bit default description
? 2014 exar corporation xr21b1422 36 / 60 exar.com/xr21b1422 rev 1a custom_driver (0x060) - write only this register determines which device driver is used (custom or cdc driver). for proper operati on, a custom driver must set the active bit prior to sending any of the 4 cdc_acm commands supported by the xr21b1422. suspend_state (0x6a) - read/write this register is used to set the stat e of gpio pins based on the setting of the use_suspend bit in the suspend_mode register. bit default description 15:1 0 reserved these bits are reserved and should be written as 0. 00 active 0: informs the xr21b1422 that the standard cdc_acm driver is being used. 1: informs the xr21b1422 that a custom driver is being used. bit default description 15:14 0 reserved these bits are reserved and should be written as 0. 13 0 dsr 0: when use_suspend is 1, clear this bit to a 0 1: when use_suspend is 1, set this bit to a 1 12 0 dtr 0: when use_suspend is 1, clear this bit to a 0 1: when use_suspend is 1, set this bit to a 1 11 0 ri 0: when use_suspend is 1, clear this bit to a 0 1: when use_suspend is 1, set this bit to a 1 10 0 cd 0: when use_suspend is 1, clear this bit to a 0 1: when use_suspend is 1, set this bit to a 1 9:8 0 reserved these bits are reserved and should be written as 0. 70 rxt 0: when use_suspend is 1, clear this bit to a 0 1: when use_suspend is 1, set this bit to a 1 60 txt 0: when use_suspend is 1, clear this bit to a 0 1: when use_suspend is 1, set this bit to a 1 5:4 0 reserved these bits are reserved and should be written as 0. 30 rs485 0: when use_suspend is 1, clear this bit to a 0 1: when use_suspend is 1, set this bit to a 1 20 cts 0: when use_suspend is 1, clear this bit to a 0 1: when use_suspend is 1, set this bit to a 1
? 2014 exar corporation xr21b1422 37 / 60 exar.com/xr21b1422 rev 1a suspend_mode (0x06b) - read/write 10 rts 0: when use_suspend is 1, clear this bit to a 0 1: when use_suspend is 1, set this bit to a 1 00 clk 0: when use_suspend is 1, clear this bit to a 0 1: when use_suspend is 1, set this bit to a 1 bit default description 15 0 use_suspend 0: gpio pins will retain output state when device is suspended 1: gpio pins will assert state defined in suspend_state and mode defined in suspend_mode when device is sus- pended. 14 0 reserved this bit is reserved and should be written as 0. 13 0 dsr 0: when use_suspend is 1, output will be actively driven 1: when use_suspend is 1, output will be open drain 12 0 dtr 0: when use_suspend is 1, output will be actively driven 1: when use_suspend is 1, output will be open drain 11 0 ri 0: when use_suspend is 1, output will be actively driven 1: when use_suspend is 1, output will be open drain 10 0 cd 0: when use_suspend is 1, output will be actively driven 1: when use_suspend is 1, output will be open drain 9:8 0 reserved these bits are reserved and should be written as 0. 70 rxt 0: when use_suspend is 1, output will be actively driven 1: when use_suspend is 1, output will be open drain 60 txt 0: when use_suspend is 1, output will be actively driven 1: when use_suspend is 1, output will be open drain 5:4 0 reserved these bits are reserved and should be written as 0. 30 rs485 0: when use_suspend is 1, output will be actively driven 1: when use_suspend is 1, output will be open drain 20 cts 0: when use_suspend is 1, output will be actively driven 1: when use_suspend is 1, output will be open drain bit default description
? 2014 exar corporation xr21b1422 38 / 60 exar.com/xr21b1422 rev 1a revision_id (0x260) - read-only usb_status (0x262) - read-only 10 rts 0: when use_suspend is 1, output will be actively driven 1: when use_suspend is 1, output will be open drain 00 clk 0: when use_suspend is 1, output will be actively driven 1: when use_suspend is 1, output will be open drain bit default description 15:0 0 revision id bit default description 15:14 0 reserved these bits are reserved and should be written as 0. 13 0 state1 returns the current state of the usb_stat2 pin. 12:10 0 sel1 000: usb_stat2 asserted high when in suspended state or when usb bus reset is asserted 001: usb_stat2 asserted high when in suspended state 010: for low power device (<= 100 ma) usb_stat2 asserted high when in suspended state. for high power device (101-500 ma) asserted high when in suspended state or when not yet configured. 011: usb_stat2 asserted high when usb bus reset is asserted 100: usb_stat2 asserted high when in suspended state or when usb bus reset is asserted 101: usb_stat2 asserted low when in suspended state 110: for low power device (<= 100 ma) usb_stat2 asserted low when in suspended state. for high power device (101-500 ma) asserted low when in suspended state or when not yet configured. 111: usb_stat2 asserted low when usb bus reset is asserted 9:8 10 ctrl1 00: invalid 01: usb_stat2 open drain 10: usb_stat2 actively driven 11: invalid 7:6 0 reserved these bits are reserved and should be written as 0. 50 state0 returns the current state of the usb_stat1 pin. bit default description
? 2014 exar corporation xr21b1422 39 / 60 exar.com/xr21b1422 rev 1a 4:2 0 sel0 000: usb_stat1 asserted low when in suspended state or when usb bus reset is asserted 001: usb_stat1 asserted high when in suspended state 010: for low power device (<= 100 ma) usb_stat1 asserted high when in suspended state. for high power device (101-500 ma) asserted high when in suspended state or when not yet configured. 011: usb_stat1 asserted high when usb bus reset is asserted 100: usb_stat1 asserted low when in suspended state or when usb bus reset is asserted 101: usb_stat1 asserted low when in suspended state 110: for low power device (<= 100 ma) usb_stat1 asserted low when in suspended state. for high power device (101-500 ma) asserted low when in suspended state or when not yet configured. 111: usb_stat1 asserted low when usb bus reset is asserted 10 ctrl0 00: invalid 01: usb_stat1 open drain 10: usb_stat1 actively driven 11: invalid 0 reserved this bit is reserved and should be written as 0. bit default description
? 2014 exar corporation xr21b1422 40 / 60 exar.com/xr21b1422 rev 1a otp map note that all otp memory locations are 8 bits wide. table 9: xr21b1422 otp memory address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x000 hw_config 0 lock reserved 0x007 cdc_acm_overrides 0 0 0 baud_- thres h gpi- o_int_ mask gpi- o_dir gpio_- mode flow 0x008 cdc_acm_flow 0 0 0 0 half- duplex mode select 0x009 cdc_acm_mode_lsb clk_en rs485_sel rs485_ pin rs485_ pol mode select 0x00a cdc_acm_mode_msb 0 0 0 0 0 0 rx_- tog tx_tog 0x00b cdc_acm_gpio_dir_lsb gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x00c cdc_acm_gpio_dir_msb 0 0 0 0 0 0 gpio9 gpio8 0x00d cdc_acm_gpi- o_int_mask_lsb gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 0x00e cdc_acm_gpi- o_int_mask_msb 00000rxgpio9gpio8 0x00f cdc_acm_baud_thresh_0 thresh[7:0] 0x010 cdc_acm_baud_thresh_1 thresh[15:8] 0x011 cdc_acm_baud_thresh_2 thresh[23:16] 0x012 vid_lsb value[7:0] 0x013 vid_msb value[15:8] 0x014 pid_lsb value[7:0] 0x015 pid_msb value[15:8] 0x016 usb_max_power value 0x017 usb_attributes 0 0 0 0 rmt_w ake_en rmt_w ake_va lid pwr_mode 0x018 release_major value 0x019 release_minor value 0x01a auto_flush 0 0 0 rx_- close rx_ope n tx_- close tx_ope n 0 0x01b lock_byte_0 lang_i d 000pin_- config ser_st rg prod_ strg2 prod_s trg1 0x01c lock_byte_1 ven_st rg2 ven_st rg1 flush rel usb_at trib max- _powe r pid vid 0x01f pin_cfg_usb_stat1 0 0 0 sel ctrl
? 2014 exar corporation xr21b1422 41 / 60 exar.com/xr21b1422 rev 1a 0x020 pin_cfg_usb_stat2 0 0 0 sel ctrl 0x024 pin_cfg_clk pullup pull_ down 000 ctrl 0x025 pin_cfg_rts pullup pull_ down 000ctrl 0x026 pin_cfg_cts pullup pull_ down 0000 ctrl 0x027 pin_cfg_rs485 pullup pull_ down 0000 ctrl 0x028 pin_cfg_txt pullup pull_ down 0000 ctrl 0x029 pin_cfg_rxt pullup pull_ down 0000 ctrl 0x02a pin_cfg_cd pullup pull_ down 0000 ctrl 0x02b pin_cfg_ri pullup pull_ down 0000 ctrl 0x02c pin_cfg_dtr pullup pull_ down 000ctrl 0x02d pin_cfg_dsr pullup pull_ down 000 ctrl 0x02e pin_cfg_data_pins pullup pull_ down rx_ rem_ wake 000 0ctrl 0x02f suspend_state (msb) 0 0 dsr dtr ri cd 0 0 0x030 suspend_state (lsb) rxt txt 0 0 rs485 cts rts clk 0x031 suspend_mode (msb) 0 0 dsr dtr ri cd 0 0 0x032 suspend_mode (lsb) rxt txt 0 0 rs485 cts rts clk 0x033 pin_cfg_rs485_pol pol 0x034 clk_div value table 9: xr21b1422 otp memory address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
? 2014 exar corporation xr21b1422 42 / 60 exar.com/xr21b1422 rev 1a otp memory descriptions some otp locations will be pre-programmed at the factory. all otp reset default va lues are 0 indicating that these bits have not been programmed. conversely a 1 in any bit position indicates that bit has been previously programmed. note: the contents of all fields, except the cdc_acm override s fields will not take effect unless the corresponding bit in the prog_byte_lsb or prog_byte_msb registers have been set. once that bit has been set, no further changes can be made to that field. caution: do not set the prog bit for any field that has not had desired data entered, otherwise, the field will be programmed with all 0s. hw_config (0x000) - read/write otp cdc_acm_overrides (0x007) - read/write otp cdc_acm override registers 0x008 - 0x00e are not described her e as the bit definitions are the same as in the equivalent register in ta bl e 5 . bit default description 70 reserved this bit is reserved and should remain 0. 60 lock 0: global lock is not set 1: global lock is set. all further writes to the otp will be di sallowed. before setting the global lock bit, user must first s et reg- ister 0x1898 to 0x10. note that global lock does not take effect until the next hardware or power on reset. 5:0 0 reserved factory programmed - overwriting these bits ma y cause functional damage to the xr21b1422 device bit default description 7:5 0 reserved these bits are reserved and should be written as 0. 40 baud_threshold 0: use default cdc-acm 1: override cdc-acm baud rate threshold defaults with the values in the cdc_acm_baud_thresh registers 30 gpio_int_mask 0: use default cdc-acm 1: override cdc-acm gpio interrupt mask defaults with the values in the cdc_acm_gpio_int_mask register 20 gpio_direction 0: use default cdc-acm 1: override cdc-acm gpio direction defaults wi th the values in the cdc_acm_dir register 10 gpio_mode 0: use default cdc-acm 1: override cdc-acm gpio mode defaults with t he values in the cdc_acm_gpio_mode register 00 flow 0: use default cdc-acm flow control 1: override cdc-acm flow control defaults with the values in the cdc_acm_flow register
? 2014 exar corporation xr21b1422 43 / 60 exar.com/xr21b1422 rev 1a cdc_acm_flow (0x008) - read/write otp cdc_acm_mode_lsb (0x009) - read/write otp bit default description 15:4 0 reserved these bits are reserved and should be written as 0. 30 uart half-duplex mode 0: normal (full-duplex) mode. the uart can transmit and receive data at the same time. 1: uart half-duplex mode. in half-duplex mode, any data on the rx pin is ignored when the uart is transmitting data. 2:0 000 mode 000: mode 0. no flow control, no address matching. 001: mode 1. hw flow control enabled. auto rts/cts or dtr/dsr must be selected by gpio_mode. 010: mode 2. sw flow control enabled. 011: mode 3. multidrop mode - rx only after address ma tch, tx independent. (typically used with gpio_mode 3). 100: mode 4. multidrop mode - rx/tx only after address match. (typically used with gpio_mode 4). 101 to 111 : re s e r ve d bit default description 70 clock enable 0: gpio6 is used for general purpose i/o 1: gpio6 is used to output a clock. 6:5 0 auto rs-485 half-duplex select 00: gpio. gpio7/rs485 is used for general purpose i/o 01: rs485_en_act. gpio7/rs485 is used for auto rs-485 half- duplex enable. asserted whenever the uart is transmitting 10: rs485_en_flow. gpio7/rs485 is used for auto rs-485 half- duplex enable. asserted for the duration of the address match 11: reserved. reserved value, do not use 40 auto rs-485 half-duplex pin 0: gpio5/rts#/rs485 function is selected by gpio_mode[2:0]. gpio7/rs485 function is gpio. 1: gpio7/rs485 function is selected by gpio_mode[6:5]. gp io5/rts#/rs485 function must be any function other than that selected for gpio7/rs485. 30 auto rs-485 half-duplex polarity 0: gpio5/rts#/rs485 function is selected by gpio_mode[2:0]. gpio7/rs485 function is gpio. 1: gpio7/rs485 function is selected by gpio_mode[6:5]. gp io5/rts#/rs485 function must be any function other than that selected for gpio7/rs485. 2:0 0 gpio mode select 000: gpio. rts/cts and dtr/dsr are used for general purpose i/o. 001: rts_cts. gpio4 and gpio5 used for auto rts/cts hw flow control 010: dtr_dsr. gpio2 and gpio3 used for auto dtr/dsr hw flow control 011: rs485_en_act. gpio5/rts#/rs485 pin used fo r auto .rs-485 half-duplex enable during transmit 100: rs485_en_flow. gpio5/rts#/rs485 pin used for auto rs-485 half-duplex enable after address match. 101 to 111: reserved. reserved value, do not use.
? 2014 exar corporation xr21b1422 44 / 60 exar.com/xr21b1422 rev 1a cdc_acm_mode_msb (0x00a) - read/write otp cdc_acm_gpio_dir_lsb (0x00b) - read/write otp cdc_acm_gpio_dir_msb (0x00c) - read/write otp cdc_acm_gpio_int_mask_lsb (0x00d) - read/write otp bit default description 7:2 0 reserved these bits are reserved and should be written as 0. 11 receive toggle 0: gpio9 is used for general purpose i/o 1: gpio9 is used to receive toggle output (default). 01 transmit toggle 0: gpio8 is used for general purpose i/o. 1: gpio8 is used to transmit toggle output (default). bit default description 7:0 0 gpio direction of gpio[9:0] 0: gpiox is an input. 1: gpiox is an output. bit default description 7:2 0 reserved these bits are reserved and should be 0. 1:0 0 gpio direction of gpio[9:0] 0: gpiox is an input. 1: gpiox is an output. bit default description 7:0 0x0 gpio interrupt mask of gpio[7:0] 0: a change in the input pin's state causes the device to generate an interrupt packet 1: a change in the input pin's state does not cause the device to generate an interrupt packet
? 2014 exar corporation xr21b1422 45 / 60 exar.com/xr21b1422 rev 1a cdc_acm_gpio_int_mask_msb (0x00e) - read/write otp cdc_acm_baud_thres_0 (0x00f) - read/write otp cdc_acm_baud_thres_1 (0x010) - read/write otp cdc_acm_baud_thres_2 (0x011) - read/write otp vid_lsb (0x012) - read/write otp bit default description 7:3 0 reserved these bits are reserved and should be written as 0. 20 gpio interrupt mask of rx 0: a change in the input pin's state causes the device to generate an interrupt packet 1: a change in the input pin's state does not cause the device to generate an interrupt packet 1:0 0x100 gpio interrupt mask of gpio[9:0] 0: a change in the input pin's state causes the device to generate an interrupt packet 1: a change in the input pin's state does not cause the device to generate an interrupt packet bit default description 7:0 0 cdc_acm_baud_thres[7:0] least significant byte of the cdc_acm baud ra te threshold override for low latency mode. bit default description 7:0 0 cdc_acm_baud_thres[15:8] second least significant byte of the cdc_acm baud rate threshold override for low latency mode. bit default description 7:0 0 cdc_acm_baud_thres[23:16] most significant byte of the cdc_acm baud rate threshold override for low latency mode. bit default description 7:0 0 vendor id[7:0] least significant byte of the vendor id.
? 2014 exar corporation xr21b1422 46 / 60 exar.com/xr21b1422 rev 1a vid_msb (0x013) - read/write otp pid_lsb (0x014) - read/write otp pid_msb (0x015) - read/write otp usb_max_power (0x016) - read/write otp usb_attributes (0x017) - read/write otp bit default description 7:0 0 vendor id[15:8] most significant byte of the vendor id. bit default description 7:0 0 product id[7:0] least significant byte of the product id. bit default description 7:0 0 product id[15:8] most significant byte of the product id. bit default description 7:0 0 usb max power the bmaxpower field of the device descriptor. maximum device power consumption from vbus power. values from 0x01 (2 ma) to 0xfa (500 ma). bit default description 7:4 0 reserved these bits are reserved and should be written as 0. 30 remote_wake_en this bit advertises if remote wakeup is enabled or disabled in d5 of bmattributes field of the configuration descriptor if the remote_wake_valid bit is set. 0: remote wakeup is disabled 1: remote wakeup is enabled 20 remote_wake_valid this bit allows the remote wakeup setting in remote_wake_en to be advertised in d5 of the bmattributes field of the con- figuration descriptor. 0: do not advertise remote wakeup setting in remote_wake_en 1: advertise remote wakeup setting in remote_wake_en
? 2014 exar corporation xr21b1422 47 / 60 exar.com/xr21b1422 rev 1a release_major (0x018) - read/write otp release_minor (0x019) - read/write otp auto_flush (0x01a) - read/write otp this register controls whether the fifo buffers are flushed on open and/or close events. 1:0 0 power_mode this field determines power mode as re ported in the configuration descriptor. 00: bus powered mode 01: self powered mode 10: self powered mode 11: invalid bit default description 7:0 0 major release bit default description 7:0 0 minor release bit default description 7:5 0 reserved these bits are reserved and should be written as 0. 40 rx_close 0: do not automatically flush the rx fifo 1: automatically flush the rx fifo when the com port is closed 30 rx_open 0: do not automatically flush the rx fifo 1: automatically flush the rx fifo when the com port is opened 20 tx_close 0: do not automatically flush the tx fifo 1: automatically flush the tx fifo when the com port is closed 10 tx_open 0: do not automatically flush the tx fifo 1: automatically flush the tx fifo when the com port is opened 00 reserved this bit is reserved and should be written as 0. bit default description
? 2014 exar corporation xr21b1422 48 / 60 exar.com/xr21b1422 rev 1a lock_byte_0 (0x01b) - read/write otp each bit field in the lock_byte_0 register must be set by the user to indicate the corresponding field has been pro- grammed. any field that has been programmed can not be programmed again. caution: do not set the prog bit for any field that has not had the entire data field entered, otherwise, the empty field or any portion thereof will be prog rammed (all 0s) into the otp. for definitions of the individual fields, refer to the corresponding register definition in xr21b1422 register map on page 21. lock_byte_1 (0x01c) - read/write otp each bit field in the lock_byte_1 register must be set by the user to indicate the corresponding field has been pro- grammed. any field that has been programmed can not be programmed again. caution: do not set the prog bit for any field that has not had the entire data field entered, otherwise, the empty field or any portion thereof will be prog rammed (all 0s) into the otp. for definitions of the individual fields, refer to the corresponding register definition in xr21b1422 register map on page 21. bit default description 70 lang_id 0: corresponding field has not been programmed. values will not be read from otp. 1: corresponding field has been programmed. values will be read from otp. 60 pin_cfg_uart3 0: corresponding field has not been programmed. values will not be read from otp. 1: corresponding field has been programmed. values will be read from otp. 50 pin_cfg_uart2 0: corresponding field has not been programmed. values will not be read from otp. 1: corresponding field has been programmed. values will be read from otp. 40 pin_cfg_uart1 0: corresponding field has not been programmed. values will not be read from otp. 1: corresponding field has been programmed. values will be read from otp. 30 pin_cfg_uart0 0: corresponding field has not been programmed. values will not be read from otp. 1: corresponding field has been programmed. values will be read from otp. 20 serial_string 0: corresponding field has not been programmed. values will not be read from otp. 1: corresponding field has been programmed. values will be read from otp. 10 prod_string_2 0: do not automatically flush the tx fifo 1: automatically flush the tx fifo when the com port is opened 00 prod_string_1 this bit is reserved and should be written as 0. bit default description 70 vend_string2 0: corresponding field has not been programmed. values will not be read from otp. 1: corresponding field has been programmed. values will be read from otp.
? 2014 exar corporation xr21b1422 49 / 60 exar.com/xr21b1422 rev 1a pin_cfg_usb_stat1 (0x01f) - read/write otp controls the configuration of the usb_stat1 pin during suspend state 60 vend_string1 0: corresponding field has not been programmed. values will not be read from otp. 1: corresponding field has been programmed. values will be read from otp. 50 flush 0: corresponding field has not been programmed. values will not be read from otp. 1: corresponding field has been programmed. values will be read from otp. 40 release 0: corresponding field has not been programmed. values will not be read from otp. 1: corresponding field has been programmed. values will be read from otp. 30 usb_attributes 0: corresponding field has not been programmed. values will not be read from otp. 1: corresponding field has been programmed. values will be read from otp. 20 max_power 0: corresponding field has not been programmed. values will not be read from otp. 1: corresponding field has been programmed. values will be read from otp. 10 pid 0: corresponding field has not been programmed. values will not be read from otp. 1: corresponding field has been programmed. values will be read from otp. 00 vid 0: corresponding field has not been programmed. values will not be read from otp. 1: corresponding field has been programmed. values will be read from otp. bit default description 7:5 0 reserved these bits are reserved and should be written as 0. 4:2 0 sel 000: assert logic 1 during suspend or usb bus_reset else logic 0 001: assert logic 1 during suspend else logic 0 010: assert logic 1 during low_pwr else logic 0 011: assert logic 1 during usb bus_reset else logic 0 100: assert logic 1 during suspend or usb bus_reset else logic 0 101: assert logic 0 during suspend else logic 1 110: assert logic 0 during low_pwr else logic 1 111: assert logic 0 during usb bus_reset else logic 1 1:0 0 ctrl 00: invalid, do not use 01: output, open drain 10: output, push-pull 11: invalid, do not use bit default description
? 2014 exar corporation xr21b1422 50 / 60 exar.com/xr21b1422 rev 1a pin_cfg_usb_stat2 (0x020) - read/write otp controls the configuration of the usb_stat2 pin during suspend state pin_cfg_clk (0x024) - read/write otp this register configures the functionality of the gpio6/clk pin. bit default description 7:5 0 reserved these bits are reserved and should be written as 0. 4:2 0 sel 000: assert logic 0 during suspend or usb bus_reset else logic 1 001: assert logic 1 during suspend else logic 0 010: assert logic 1 during low_pwr else logic 0 011: assert logic 1 during usb bus_reset else logic 0 100: assert logic 0 during suspend or usb bus_reset else logic 1 101: assert logic 0 during suspend else logic 1 110: assert logic 0 during low_pwr else logic 1 111: assert logic 0 during usb bus_reset else logic 1 1:0 0 ctrl 00: invalid, do not use 01: output, open drain 10: output, push-pull 11: invalid, do not use bit default description 70 pullup_en this register bit is used to enable the internal pull-up resist or. this setting will be ignored if gpio6/clk is configured as a n output. 0: do not enable internal pull-up 1: enable internal pull-up if configured as an input 60 pulldown_en this register bit is used to enable the internal pull-down resi stor. this setting will be ignored if gpio6/clk is configured as an output. 0: do not enable internal pull-down 1: enable internal pull-down if configured as an input (will not be enabled if pull up is enabled) 5:2 0 reserved these bits are reserved and should be written as 0. 1:0 0 ctrl 00: gpio6/clk is configured as a gpio input 01: gpio6/clk is configured as a gpio open drain output 10: gpio6/clk is configured as a gpio push-pull output 11: gpio6/clk is configured as a push-pull clk output
? 2014 exar corporation xr21b1422 51 / 60 exar.com/xr21b1422 rev 1a pin_cfg_rts (0x025) - read/write otp this register configures the functionality of the gpio5/rts#/rs485 pin. pin_cfg_cts (0x026) - read/write otp this register configures the functionality of the gpio4/cts# pin. bit default description 70 pullup_en this register bit is used to enable the in ternal pull-up resistor. this setting will be ignored if gpio5/rts#/rs485 is configur ed as an output. 0: do not enable internal pull-up 1: enable internal pull-up if configured as an input 60 pulldown_en this register bit is used to enable the internal pull-down resi stor. this setting will be ignored if gpio5/rts#/rs485 is config - ured as an output. 0: do not enable internal pull-down 1: enable internal pull-down if configured as an input (will not be enabled if pull up is enabled) 5:3 0 reserved these bits are reserved and should be written as 0. 2:0 0 ctrl note: if configured as rts output, gpio4/cts# must be c onfigured as cts input and gpio2/dsr# and gpio3/dtr# must be configured as gpios. 000: gpio5/rts#/rs485 is configured as a gpio input 001: gpio5/rts#/rs485 is configured as a gpio open drain output 010: gpio5/rts#/rs485 is conf igured as a gpio push-pull output 011: gpio5/rts#/rs485 is configured as a open drain rts output 100: gpio5/rts#/rs485 is configured as a push-pull rts output bit default description 70 pullup_en this register bit is used to enable the internal pull-up resistor . this setting will be ignored if gpio4/cts# is configured as an output. 0: do not enable internal pull-up 1: enable internal pull-up if configured as an input 60 pulldown_en this register bit is used to enable the internal pull-down resi stor. this setting will be ignored if gpio4/cts# is configured a s an output. 0: do not enable internal pull-down 1: enable internal pull-down if configured as an input (will not be enabled if pull up is enabled) 5:2 0 reserved these bits are reserved and should be written as 0. 1:0 0 ctrl note: if configured as cts input, gpio5/rts# must be configured as rts# output and gpio2/dsr# and gpio3/dtr# must be configured as gpios. 00: gpio4/cts# is configured as a gpio input 01: gpio4/cts# is configured as a gpio open drain output 10: gpio4/cts# is configur ed as a gpio push-pull output 11: gpio4/cts# is configur ed as a open drain cts input
? 2014 exar corporation xr21b1422 52 / 60 exar.com/xr21b1422 rev 1a pin_cfg_rs485 (0x027) - read/write otp this register configures the functionality of the gpio7/rs485 pin pin_cfg_txt (0x028) - read/write otp this register configures the functionality of the gpio8/txt pin bit default description 70 pullup_en this register bit is used to enable the internal pull-up resistor. this setting wi ll be ignored if gpio7/rs485 is configured as an output. 0: do not enable internal pull-up 1: enable internal pull-up if configured as an input 60 pulldown_en this register bit is used to enable the internal pull-down resi stor. this setting will be ignored if gpio7/rs485 is configured as an output. 0: do not enable internal pull-down 1: enable internal pull-down if configured as an input (will not be enabled if pull up is enabled) 5:2 0 reserved these bits are reserved and should be written as 0. 1:0 0 ctrl note: if configured as cts input, gpio5/rts# must be configured as rts# output and gpio2/dsr# and gpio3/dtr# must be configured as gpios. 00: gpio7/rs485 is configured as a gpio input 01: gpio7/rs485 is configured as a gpio open drain output 10: gpio7/rs485 is configured as a gpio push-pull output 11: gpio7/rs485 is configured as a push- pull auto. rs-485 half-duplex enable output bit default description 70 pullup_en this register bit is used to enable the internal pull-up resist or. this setting will be ignored if gpio8/txt is configured as a n output. 0: do not enable internal pull-up 1: enable internal pull-up if configured as an input 60 pulldown_en this register bit is used to enable the internal pull-down resi stor. this setting will be ignor ed if gpio8/txt is configured as an output. 0: do not enable internal pull-down 1: enable internal pull-down if configured as an input (will not be enabled if pull up is enabled) 5:2 0 reserved these bits are reserved and should be written as 0. 1:0 0 ctrl 00: gpio8/txt is configured as a gpio input 01: gpio8/txt is configured as a gpio open drain output 10: gpio8/txt is configured as a gpio push-pull output 11: gpio8/txt is configured as a push-pull tx toggle output
? 2014 exar corporation xr21b1422 53 / 60 exar.com/xr21b1422 rev 1a pin_cfg_rxt (0x029) - read/write otp this register configures the functionality of the gpio9/rxt pin pin_cfg_cd (0x02a) - read/write otp this register configures the functionality of the gpio1/cd pin bit default description 70 pullup_en this register bit is used to enable the internal pull-up resistor . this setting will be ignored if gpio9/rxt is configured as a n output. 0: do not enable internal pull-up 1: enable internal pull-up if configured as an input 60 pulldown_en this register bit is used to enable the internal pull-down resi stor. this setting will be ignored if gpio9/rxt is configured as an output. 0: do not enable internal pull-down 1: enable internal pull-down if configured as an input (will not be enabled if pull up is enabled) 5:2 0 reserved these bits are reserved and should be written as 0. 1:0 0 ctrl 000: gpio9/rxt is configured as a gpio input 001: gpio9/rxt is configured as a gpio open drain output 010: gpio9/rxt is configur ed as a gpio push-pull output 011: gpio9/rxt is configured as a push-pull rx toggle output bit default description 70 pullup_en this register bit is used to enable the internal pull-up resistor . this setting will be ignored if gpio1/cd# is configured as a n output. 0: do not enable internal pull-up 1: enable internal pull-up if configured as an input 60 pulldown_en this register bit is used to enable the internal pull-down resi stor. this setting will be ignored if gpio1/cd# is configured as an output. 0: do not enable internal pull-down 1: enable internal pull-down if configured as an input (will not be enabled if pull up is enabled) 5:2 0 reserved these bits are reserved and should be written as 0. 1:0 0 ctrl 00: gpio1/cd# is configured as a gpio input 01: gpio1/cd# is configured as a gpio open drain output 10: gpio1/cd# is configured as a gpio push-pull output 11: invalid, do not use
? 2014 exar corporation xr21b1422 54 / 60 exar.com/xr21b1422 rev 1a pin_cfg_ri (0x02b) - read/write otp this register configures the functionality of the gpio0/ri pin pin_cfg_dtr (0x02c) - read/write otp this register configures the functionality of the gpio3/dtr pin bit default description 70 pullup_en this register bit is used to enable the in ternal pull-up resistor. this setting will be ignored if gpio0/ri#/rwk# is configured as an output. 0: do not enable internal pull-up 1: enable internal pull-up if configured as an input 60 pulldown_en this register bit is used to enable the internal pull-down resi stor. this setting will be ignored if gpio0/ri#/rwk# is configur ed as an output. 0: do not enable internal pull-down 1: enable internal pull-down if configured as an input (will not be enabled if pull up is enabled) 5:2 0 reserved these bits are reserved and should be written as 0. 1:0 0 ctrl 00: gpio0/ri#/rwk# is configured as a gpio input 01: gpio0/ri#/rwk# is configured as a gpio open drain output 10: gpio0/ri#/rwk# is config ured as a gpio push-pull output 11 to 111: invalid, do not use bit default description 70 pullup_en this register bit is used to enable the internal pull-up resist or. this setting will be ignored if gpio3/dtr# is configured as an output. 0: do not enable internal pull-up 1: enable internal pull-up if configured as an input 60 pulldown_en this register bit is used to enable the internal pull-down resi stor. this setting will be ignored if gpio3/dtr# is configured a s an output. 0: do not enable internal pull-down 1: enable internal pull-down if configured as an input (will not be enabled if pull up is enabled) 5:3 0 reserved these bits are reserved and should be written as 0. 2:0 0 ctrl note: if configured as dtr output, gpio2/dsr# must be configured as dsr input an d gpio5/rts#/rs485 and gpio4/ cts# must be configured as gpios. 000: gpio3/dtr is configured as a gpio input 001: gpio3/dtr is configured as a gpio open drain output 010: gpio3/dtr is configured as a gpio push-pull output 011: gpio3/dtr is configured as a open drain dtr output 100: gpio3/dtr is configur ed as a push-pull dtr output 101 to 111: invalid, do not use
? 2014 exar corporation xr21b1422 55 / 60 exar.com/xr21b1422 rev 1a pin_cfg_dsr (0x02d) - read/write otp this register configures the functionality of the gpio2/dsr pin pin_cfg_data_pins (0x02e) - read/write otp this register configures the functionality of the rx and tx data pins bit default description 70 pullup_en this register bit is used to enable the internal pull-up resist or. this setting will be ignored if gpio3/dtr# is configured as an output. 0: do not enable internal pull-up 1: enable internal pull-up if configured as an input 60 pulldown_en this register bit is used to enable the internal pull-down resi stor. this setting will be ignored if gpio3/dtr# is configured a s an output. 0: do not enable internal pull-down 1: enable internal pull-down if configured as an input (will not be enabled if pull up is enabled) 5:2 0 reserved these bits are reserved and should be written as 0. 1:0 0 ctrl 00: gpio2/dsr# is configured as a gpio input 01: gpio2/dsr# is configured as a gpio open drain output 10: gpio2/dsr# is configured as a gpio push-pull output 11 to 111: invalid, do not use bit default description 70 rx_pullup_en this register bit is used to enabled the internal pull-up on the rx pin 0: do not enable internal pull-up on rx pin 1: enable internal pull-up on rx pin 60 rx_pulldown_en this register bit is used to enabled the internal pull-down on the rx pin 0: do not enable internal pull-down on rx pin 1: enable internal pull-down on rx pin (will not be enabled if pull-up is enabled) 50 rx_remote_wake_en this register bit enables remote wakeup capability on the rx pin 0: rx pin is not enabled for remote wakeup 1: rx pin is enabled for remote wakeup if global remote wakeup is enabled 4:1 0 reserved these bits are reserved and should be written as 0. 00 tx_ctrl 0: tx open drain output 1: tx push-pull output
? 2014 exar corporation xr21b1422 56 / 60 exar.com/xr21b1422 rev 1a suspend_state_msb (0x02f) - read/write otp this register configures the state of the gpio pins during su spend state. note that rx and tx data pins are not controlled by suspend_state. use_suspend is not a physical pin, but in stead acts as the control for pins in the suspended state and is in the most si gnificant bit position of suspend_mode_msb. suspend_state_lsb (0x030) - read/write otp this register configures the state of the gpio pins during suspend state. bit default description 70 gpio9/rxt 0: corresponding bit set to logic 0 during suspend if use_suspend = 1 1: corresponding bit set to logic 1 during suspend if use_suspend = 1 60 gpio8/txt 0: corresponding bit set to logic 0 during suspend if use_suspend = 1 1: corresponding bit set to logic 1 during suspend if use_suspend = 1 5:4 0 not used 30 gpio7/rs485 0: corresponding bit set to logic 0 during suspend if use_suspend = 1 1: corresponding bit set to logic 1 during suspend if use_suspend = 1 20 gpio4/cts# 0: corresponding bit set to logic 0 during suspend if use_suspend = 1 1: corresponding bit set to logic 1 during suspend if use_suspend = 1 10 gpio5/rts#/rs485 0: corresponding bit set to logic 0 during suspend if use_suspend = 1 1: corresponding bit set to logic 1 during suspend if use_suspend = 1 00 gpio6/clk 0: corresponding bit set to logic 0 during suspend if use_suspend = 1 1: corresponding bit set to logic 1 during suspend if use_suspend = 1 bit default description 7:6 0 not used 50 gpio2/dsr# 0: corresponding bit set to logic 0 during suspend if use_suspend = 1 1: corresponding bit set to logic 1 during suspend if use_suspend = 1 40 gpio3/dtr# 0: corresponding bit set to logic 0 during suspend if use_suspend = 1 1: corresponding bit set to logic 1 during suspend if use_suspend = 1 30 gpio0/ri# 0: corresponding bit set to logic 0 during suspend if use_suspend = 1 1: corresponding bit set to logic 1 during suspend if use_suspend = 1 20 gpio1/cd# 0: corresponding bit set to logic 0 during suspend if use_suspend = 1 1: corresponding bit set to logic 1 during suspend if use_suspend = 1 1:0 0 not used
? 2014 exar corporation xr21b1422 57 / 60 exar.com/xr21b1422 rev 1a suspend_mode_msb (0x031) - read/write otp this register configures the mode of the gpio pins during suspend state. note that rx and tx data pins are not controlled by suspend_state. use_suspend is not a physical pin, but in stead acts as the control for pins in the suspended state and is in the most si gnificant bit position of suspend_mode_msb. suspend_mode_lsb (0x032) - read/write otp this register configures the state of the gpio pins during suspend state. bit default description 70 gpio9/rxt 0: corresponding gpio is push-pull output during suspend if use_suspend = 1 1: corresponding gpio is open-drain output during suspend if use_suspend = 1 60 gpio8/txt 0: corresponding gpio is push-pull output during suspend if use_suspend = 1 1: corresponding gpio is open-drain output during suspend if use_suspend = 1 5:4 0 not used 30 gpio7/rs485 0: corresponding gpio is push-pull output during suspend if use_suspend = 1 1: corresponding gpio is open-drain output during suspend if use_suspend = 1 20 gpio4/cts# 0: corresponding gpio is push-pull output during suspend if use_suspend = 1 1: corresponding gpio is open-drain output during suspend if use_suspend = 1 10 gpio5/rts#/rs485 0: corresponding gpio is push-pull output during suspend if use_suspend = 1 1: corresponding gpio is open-drain output during suspend if use_suspend = 1 00 gpio6/clk 0: corresponding gpio is push-pull output during suspend if use_suspend = 1 1: corresponding gpio is open-drain output during suspend if use_suspend = 1 bit default description 70 use_suspend 0: corresponding gpio is push-pull output during suspend if use_suspend = 1 1: corresponding gpio is open-drain output during suspend if use_suspend = 1 60 not used 50 gpio2/dsr# 0: corresponding gpio is push-pull output during suspend if use_suspend = 1 1: corresponding gpio is open-drain output during suspend if use_suspend = 1 40 gpio3/dtr# 0: corresponding gpio is push-pull output during suspend if use_suspend = 1 1: corresponding gpio is open-drain output during suspend if use_suspend = 1 30 gpio0/ri# 0: corresponding gpio is push-pull output during suspend if use_suspend = 1 1: corresponding gpio is open-drain output during suspend if use_suspend = 1 20 gpio1/cd# 0: corresponding gpio is push-pull outupt during suspend if use_suspend = 1 1: corresponding bit set to logic 1 during suspend if use_suspend = 1
? 2014 exar corporation xr21b1422 58 / 60 exar.com/xr21b1422 rev 1a pin_cfg_rs485_pol (0x033) - read/write otp this register configures the polarity of the selected auto rs-485 half-duplex control pin. clk_div (0x034) - read/write otp this register sets the default clock divisor for the clk output. application circuits the gpio inputs are 5v tolerant. however, when gpio input voltage levels exceed vio, an external clamp circuit is required to prevent vio from increasing. two examples of different application circuits are shown in figure 7 . vio clamp circuits figure 7: vio clamp circuits 1:0 0 not used bit default description 7:1 0 reserved these bits are reserved and should be written as 0. 00 pol 0: active low auto. rs-485 half-duplex enable 1: active high auto. rs-485 half-duplex enable bit default description 7:0 0 value output clock frequency will be determined by the formula: freq = 24 mhz / 2 * (value). if value = 0, freq = 24 mhz bit default description

mechanical dimensions 40-pin qfn ? ?
? 2014 exar corporation xr21b1422 60 / 60 exar.com/xr21b1422 rev 1a for further assistance: email: uarttechsupport@exar.com exar technical documentation: http://www.exar.com/techdoc/ exar corporation headquarters and sales offices 48720 kato road tel: +1 (510) 668-7000 fremont, ca 95438 - usa fax: +1 (510) 668-7001 notice exar corporation reserves the right to make changes to the produc ts contained in this publication in order to improve design, p erformance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no re sponsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its product s in life support applications where the failure or malfunctio n of the product can reasonably be expected to cause failure of the life support system or to significantly af fect its safety or effectiveness. products are not authorized fo r use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user as sumes all such risks; (c) potential liability of exar cor- poration is adequately protected under the circumstances. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. ordering information revision history part number package green operating temperature range packaging quantity marking XR21B1422IL40-F 40-pin qfn yes -40c to +85c 490 / tray xr1422il xr21b1422il40tr-f 40-pin qfn yes -40c to +85c 3000 / reel xr1422il revision date description 1a november 2014 initial release. [ecn ? 1447 \ 05 ? nov ? 18 ? 2014]

▲Up To Search▲

Price & Availability of XR21B1422IL40-F

	To Download XR21B1422IL40-F Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .